[llvm] 64ce15a - AArch64/GlobalISel: Regenerate test checks
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 13 17:30:35 PST 2023
Author: Matt Arsenault
Date: 2023-01-13T20:30:30-05:00
New Revision: 64ce15a1361d618ed89f306a252e0c4f2da64164
URL: https://github.com/llvm/llvm-project/commit/64ce15a1361d618ed89f306a252e0c4f2da64164
DIFF: https://github.com/llvm/llvm-project/commit/64ce15a1361d618ed89f306a252e0c4f2da64164.diff
LOG: AArch64/GlobalISel: Regenerate test checks
Added:
Modified:
llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
index bd09e01d41fe2..f29930b54ca95 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-load-metadata.ll
@@ -4,11 +4,12 @@
define i32 @load_invariant(ptr %ptr) {
; CHECK-LABEL: name: load_invariant
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load (s32) from %ir.ptr)
- ; CHECK: $w0 = COPY [[LOAD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (invariant load (s32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !invariant.load !0
ret i32 %load
}
@@ -16,11 +17,12 @@ define i32 @load_invariant(ptr %ptr) {
define i32 @load_volatile_invariant(ptr %ptr) {
; CHECK-LABEL: name: load_volatile_invariant
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (volatile invariant load (s32) from %ir.ptr)
- ; CHECK: $w0 = COPY [[LOAD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (volatile invariant load (s32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load volatile i32, ptr %ptr, align 4, !invariant.load !0
ret i32 %load
}
@@ -28,11 +30,12 @@ define i32 @load_volatile_invariant(ptr %ptr) {
define i32 @load_dereferenceable(ptr dereferenceable(4) %ptr) {
; CHECK-LABEL: name: load_dereferenceable
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (dereferenceable load (s32) from %ir.ptr)
- ; CHECK: $w0 = COPY [[LOAD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (dereferenceable load (s32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4
ret i32 %load
}
@@ -40,11 +43,12 @@ define i32 @load_dereferenceable(ptr dereferenceable(4) %ptr) {
define i32 @load_dereferenceable_invariant(ptr dereferenceable(4) %ptr) {
; CHECK-LABEL: name: load_dereferenceable_invariant
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (dereferenceable invariant load (s32) from %ir.ptr)
- ; CHECK: $w0 = COPY [[LOAD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (dereferenceable invariant load (s32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !invariant.load !0
ret i32 %load
}
@@ -52,11 +56,12 @@ define i32 @load_dereferenceable_invariant(ptr dereferenceable(4) %ptr) {
define i32 @load_nontemporal(ptr %ptr) {
; CHECK-LABEL: name: load_nontemporal
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (non-temporal load (s32) from %ir.ptr)
- ; CHECK: $w0 = COPY [[LOAD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (non-temporal load (s32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !nontemporal !0
ret i32 %load
}
@@ -64,11 +69,12 @@ define i32 @load_nontemporal(ptr %ptr) {
define i32 @load_falkor_strided_access(ptr %ptr) {
; CHECK-LABEL: name: load_falkor_strided_access
; CHECK: bb.1 (%ir-block.0):
- ; CHECK: liveins: $x0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
- ; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load (s32) from %ir.ptr)
- ; CHECK: $w0 = COPY [[LOAD]](s32)
- ; CHECK: RET_ReallyLR implicit $w0
+ ; CHECK-NEXT: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: ("aarch64-strided-access" load (s32) from %ir.ptr)
+ ; CHECK-NEXT: $w0 = COPY [[LOAD]](s32)
+ ; CHECK-NEXT: RET_ReallyLR implicit $w0
%load = load i32, ptr %ptr, align 4, !falkor.strided.access !0
ret i32 %load
}
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