[llvm] c9ab87d - [AArch64] Add some tests for vscale being a power 2. NFC

[David Green via llvm-commits]

Author: David Green
Date: 2023-01-13T16:09:47Z
New Revision: c9ab87df9dce9aa5da1daf4a3d1f43076733e5f2

URL: https://github.com/llvm/llvm-project/commit/c9ab87df9dce9aa5da1daf4a3d1f43076733e5f2
DIFF: https://github.com/llvm/llvm-project/commit/c9ab87df9dce9aa5da1daf4a3d1f43076733e5f2.diff

LOG: [AArch64] Add some tests for vscale being a power 2. NFC

Added: 
    llvm/test/CodeGen/AArch64/vscale-power-of-two.ll

Modified: 
    

Removed: 
    


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diff  --git a/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll b/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll
new file mode 100644
index 000000000000..0d58f98f477b
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/vscale-power-of-two.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-none-eabi -mattr=+sve -verify-machineinstrs < %s | FileCheck %s
+
+define i64 @vscale_lshr(i64 %TC) {
+; CHECK-LABEL: vscale_lshr:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rdvl x8, #1
+; CHECK-NEXT:    lsr x8, x8, #4
+; CHECK-NEXT:    lsr x8, x8, #3
+; CHECK-NEXT:    udiv x9, x0, x8
+; CHECK-NEXT:    msub x0, x9, x8, x0
+; CHECK-NEXT:    ret
+  %vscale = call i64 @llvm.vscale.i64()
+  %shifted = lshr i64 %vscale, 3
+  %urem = urem i64 %TC, %shifted
+  ret i64 %urem
+}
+
+define i64 @vscale(i64 %TC) {
+; CHECK-LABEL: vscale:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    rdvl x8, #1
+; CHECK-NEXT:    lsr x8, x8, #4
+; CHECK-NEXT:    udiv x9, x0, x8
+; CHECK-NEXT:    msub x0, x9, x8, x0
+; CHECK-NEXT:    ret
+  %vscale = call i64 @llvm.vscale.i64()
+  %urem = urem i64 %TC, %vscale
+  ret i64 %urem
+}
+
+define i64 @vscale_shl(i64 %TC) {
+; CHECK-LABEL: vscale_shl:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    cnth x8
+; CHECK-NEXT:    udiv x9, x0, x8
+; CHECK-NEXT:    msub x0, x9, x8, x0
+; CHECK-NEXT:    ret
+  %vscale = call i64 @llvm.vscale.i64()
+  %shifted = shl i64 %vscale, 3
+  %urem = urem i64 %TC, %shifted
+  ret i64 %urem
+}
+
+declare i64 @llvm.vscale.i64()