[PATCH] D141697: [P10] Fix the implementation for BRH
Lei Huang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 13 08:09:20 PST 2023
lei created this revision.
lei added reviewers: power-llvm-team, amyk, maryammo.
Herald added subscribers: hiraditya, nemanjai.
Herald added a project: All.
lei requested review of this revision.
Herald added a project: LLVM.
Fixes the patterns for the brh instruction to include a clrldi when emitted.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D141697
Files:
llvm/lib/Target/PowerPC/PPCInstrP10.td
llvm/test/CodeGen/PowerPC/p10-bswap.ll
Index: llvm/test/CodeGen/PowerPC/p10-bswap.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/p10-bswap.ll
+++ llvm/test/CodeGen/PowerPC/p10-bswap.ll
@@ -12,7 +12,7 @@
; CHECK-LABEL: test_nomem16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: brh r3, r3
-; CHECK-NEXT: clrldi r3, r3, 32
+; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
entry:
%0 = tail call i16 @llvm.bswap.i16(i16 %a)
@@ -38,7 +38,7 @@
; CHECK-LABEL: test_bswap_shift16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: brh r3, r3
-; CHECK-NEXT: clrldi r3, r3, 32
+; CHECK-NEXT: clrldi r3, r3, 48
; CHECK-NEXT: blr
entry:
%0 = tail call i32 @llvm.bswap.i32(i32 %a)
@@ -59,6 +59,7 @@
; CHECK-NEXT: .cfi_offset lr, 16
; CHECK-NEXT: bl call_1 at notoc
; CHECK-NEXT: brh r3, r3
+; CHECK-NEXT: rldicl r3, r3, 0, 48
; CHECK-NEXT: sth r3, 0(r3)
bb:
switch i32 undef, label %bb1 [
Index: llvm/lib/Target/PowerPC/PPCInstrP10.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -1745,8 +1745,7 @@
def XVTLSBB : XX2_BF3_XO5_XB6_XO9<60, 2, 475, (outs crrc:$BF), (ins vsrc:$XB),
"xvtlsbb $BF, $XB", IIC_VecGeneral, []>;
def BRH : XForm_11<31, 219, (outs gprc:$RA), (ins gprc:$RS),
- "brh $RA, $RS", IIC_IntRotate,
- [(set i32:$RA, (srl (bswap i32:$RS), (i32 16)))]>;
+ "brh $RA, $RS", IIC_IntRotate, []>;
def BRW : XForm_11<31, 155, (outs gprc:$RA), (ins gprc:$RS),
"brw $RA, $RS", IIC_IntRotate,
[(set i32:$RA, (bswap i32:$RS))]>;
@@ -1991,7 +1990,10 @@
(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_lt)>;
def : Pat<(i32 (int_ppc_vsx_xvtlsbb v16i8:$XB, 0)),
(EXTRACT_SUBREG (XVTLSBB (COPY_TO_REGCLASS $XB, VSRC)), sub_eq)>;
-
+ def : Pat<(srl (bswap i32:$RS), (i32 16)),
+ (RLDICL_32 (BRH $RS), 0, 48)>;
+ def : Pat<(i64 (zext (i32 (srl (bswap i32:$RS), (i32 16))))),
+ (RLDICL_32_64 (BRH $RS), 0, 48)>;
def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 8)),
(v1i128 (COPY_TO_REGCLASS (LXVRBX ForceXForm:$src), VRRC))>;
def : Pat <(v1i128 (PPClxvrzx ForceXForm:$src, 16)),
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