[llvm] d86f1a9 - [AArch64] Update 2 RME MEC instruction encodings

[Keith Walker via llvm-commits]

Author: Keith Walker
Date: 2023-01-13T15:20:10Z
New Revision: d86f1a982e8423a2ae5a424906f6960576c35606

URL: https://github.com/llvm/llvm-project/commit/d86f1a982e8423a2ae5a424906f6960576c35606
DIFF: https://github.com/llvm/llvm-project/commit/d86f1a982e8423a2ae5a424906f6960576c35606.diff

LOG: [AArch64] Update 2 RME MEC instruction encodings

The encodings of these 2 RME MEC instructions are
incorrect and need swapping:

- DC CIPAE
- DC CIGDPAE

The correct encoding is:

Operation       op0     op1     CRn     CRm     op2
DC CIPAE, Xt    0b01    0b100   0b0111  0b1110  0b000
DC CIGDPAE, Xt  0b01    0b100   0b0111  0b1110  0b111

Differential Revision: https://reviews.llvm.org/D141689

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SystemOperands.td
    llvm/test/MC/AArch64/armv9a-mec.s
    llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index bb27683bc7bc9..7c925f0862199 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -168,8 +168,8 @@ def : DC<"GZVA",    0b011, 0b0111, 0b0100, 0b100>;
 }
 
 let Requires = [{ {AArch64::FeatureMEC} }] in {
-def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b000>;
-def : DC<"CIPAE",   0b100, 0b0111, 0b1110, 0b111>;
+def : DC<"CIPAE",   0b100, 0b0111, 0b1110, 0b000>;
+def : DC<"CIGDPAE", 0b100, 0b0111, 0b1110, 0b111>;
 }
 
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/test/MC/AArch64/armv9a-mec.s b/llvm/test/MC/AArch64/armv9a-mec.s
index e3f30f8eb783f..f2a5fe8d38fff 100644
--- a/llvm/test/MC/AArch64/armv9a-mec.s
+++ b/llvm/test/MC/AArch64/armv9a-mec.s
@@ -49,8 +49,8 @@
 // CHECK-NO-MEC: [[@LINE-2]]:15: error: expected writable system register or pstate
 
           dc cigdpae, x0
-// CHECK: dc cigdpae, x0             // encoding: [0x00,0x7e,0x0c,0xd5]
+// CHECK: dc cigdpae, x0             // encoding: [0xe0,0x7e,0x0c,0xd5]
 // CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIGDPAE requires: mec
           dc cipae, x0
-// CHECK: dc cipae, x0               // encoding: [0xe0,0x7e,0x0c,0xd5]
+// CHECK: dc cipae, x0               // encoding: [0x00,0x7e,0x0c,0xd5]
 // CHECK-NO-MEC: [[@LINE-2]]:14: error: DC CIPAE requires: mec

diff  --git a/llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt b/llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt
index ef75da0e61d1f..d1cbfcdd08342 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv9a-mec.txt
@@ -47,9 +47,9 @@
 [0x20,0xaa,0x1e,0xd5]
 # CHECK: msr MECID_RL_A_EL3, x0
 # CHECK-NO-MEC: msr S3_6_C10_C10_1, x0
-[0x00,0x7e,0x0c,0xd5]
-# CHECK: dc cigdpae, x0
-# CHECK-NO-MEC: sys #4, c7, c14, #0, x0
 [0xe0,0x7e,0x0c,0xd5]
-# CHECK: dc cipae, x0
+# CHECK: dc cigdpae, x0
 # CHECK-NO-MEC: sys #4, c7, c14, #7, x0
+[0x00,0x7e,0x0c,0xd5]
+# CHECK: dc cipae, x0
+# CHECK-NO-MEC: sys #4, c7, c14, #0, x0