[llvm] 75d43d3 - [ARM] Accept two-register form of vnmul

[Oliver Stannard via llvm-commits]

Author: Jirui Wu
Date: 2023-01-13T15:16:41Z
New Revision: 75d43d383450def4d2e373ddc9cdd829302b2bff

URL: https://github.com/llvm/llvm-project/commit/75d43d383450def4d2e373ddc9cdd829302b2bff
DIFF: https://github.com/llvm/llvm-project/commit/75d43d383450def4d2e373ddc9cdd829302b2bff.diff

LOG: [ARM] Accept two-register form of vnmul

The previous vnmul only accepts three registers. It should accept either
two or three registers as vmul does.

Differential Revision: https://reviews.llvm.org/D141405

Added: 
    

Modified: 
    llvm/lib/Target/ARM/ARMInstrVFP.td
    llvm/test/MC/ARM/fullfp16.s
    llvm/test/MC/ARM/simple-fp-encoding.s
    llvm/test/MC/Disassembler/ARM/fp-encoding.txt
    llvm/test/MC/Disassembler/ARM/fullfp16-arm.txt
    llvm/test/MC/Disassembler/ARM/fullfp16-thumb.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td
index 8be35c81420b0..c1fecf3673a0b 100644
--- a/llvm/lib/Target/ARM/ARMInstrVFP.td
+++ b/llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -496,12 +496,14 @@ def VMULH  : AHbI<0b11100, 0b10, 0, 0,
                   [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
              Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>;
 
+let TwoOperandAliasConstraint = "$Dn = $Dd" in
 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
                   (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
                   IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
                   [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>,
              Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>;
 
+let TwoOperandAliasConstraint = "$Sn = $Sd" in
 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
                   (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
                   IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
@@ -512,6 +514,7 @@ def VNMULS : ASbI<0b11100, 0b10, 1, 0,
   let D = VFPNeonA8Domain;
 }
 
+let TwoOperandAliasConstraint = "$Sn = $Sd" in
 def VNMULH : AHbI<0b11100, 0b10, 1, 0,
                   (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
                   IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",

diff  --git a/llvm/test/MC/ARM/fullfp16.s b/llvm/test/MC/ARM/fullfp16.s
index d9149ee150e7d..fcb5d83845663 100644
--- a/llvm/test/MC/ARM/fullfp16.s
+++ b/llvm/test/MC/ARM/fullfp16.s
@@ -23,6 +23,10 @@
 @ ARM:   vnmul.f16 s0, s1, s0        @ encoding: [0xc0,0x09,0x20,0xee]
 @ THUMB: vnmul.f16 s0, s1, s0        @ encoding: [0x20,0xee,0xc0,0x09]
 
+         vnmul.f16     s0, s1
+@ ARM:   vnmul.f16 s0, s0, s1       @ encoding: [0x60,0x09,0x20,0xee]
+@ THUMB: vnmul.f16 s0, s0, s1       @ encoding: [0x20,0xee,0x60,0x09]
+
          vmla.f16        s1, s2, s0
 @ ARM:   vmla.f16 s1, s2, s0         @ encoding: [0x00,0x09,0x41,0xee]
 @ THUMB: vmla.f16 s1, s2, s0         @ encoding: [0x41,0xee,0x00,0x09]

diff  --git a/llvm/test/MC/ARM/simple-fp-encoding.s b/llvm/test/MC/ARM/simple-fp-encoding.s
index 74babf9a699a6..22bc30498fc70 100644
--- a/llvm/test/MC/ARM/simple-fp-encoding.s
+++ b/llvm/test/MC/ARM/simple-fp-encoding.s
@@ -34,9 +34,13 @@
 
         vnmul.f64       d16, d17, d16
         vnmul.f32       s0, s1, s0
+        vnmul.f64       d0, d1
+        vnmul.f32       s0, s1
 
 @ CHECK: vnmul.f64 d16, d17, d16     @ encoding: [0xe0,0x0b,0x61,0xee]
 @ CHECK: vnmul.f32 s0, s1, s0        @ encoding: [0xc0,0x0a,0x20,0xee]
+@ CHECK: vnmul.f64 d0, d0, d1        @ encoding: [0x41,0x0b,0x20,0xee]
+@ CHECK: vnmul.f32 s0, s0, s1        @ encoding: [0x60,0x0a,0x20,0xee]
 
         vcmp.f64       d17, d16
         vcmp.f32       s1, s0

diff  --git a/llvm/test/MC/Disassembler/ARM/fp-encoding.txt b/llvm/test/MC/Disassembler/ARM/fp-encoding.txt
index 196bf44d4af3d..beccce813e380 100644
--- a/llvm/test/MC/Disassembler/ARM/fp-encoding.txt
+++ b/llvm/test/MC/Disassembler/ARM/fp-encoding.txt
@@ -27,9 +27,15 @@
 0xe0 0x0b 0x61 0xee
 # CHECK: vnmul.f64       d16, d17, d16
 
+0x41 0x0b 0x20 0xee
+# CHECK: vnmul.f64       d0, d0, d1
+
 0xc0 0x0a 0x20 0xee
 # CHECK: vnmul.f32       s0, s1, s0
 
+0x60 0x0a 0x20 0xee
+# CHECK: vnmul.f32       s0, s0, s1
+
 0xe0 0x1b 0xf4 0xee
 # CHECK: vcmpe.f64       d17, d16
 

diff  --git a/llvm/test/MC/Disassembler/ARM/fullfp16-arm.txt b/llvm/test/MC/Disassembler/ARM/fullfp16-arm.txt
index 8a7ce68933eb3..c40a374c5af29 100644
--- a/llvm/test/MC/Disassembler/ARM/fullfp16-arm.txt
+++ b/llvm/test/MC/Disassembler/ARM/fullfp16-arm.txt
@@ -15,6 +15,9 @@
 # CHECK:        vnmul.f16       s0, s1, s0
 [0xc0,0x09,0x20,0xee]
 
+# CHECK:        vnmul.f16       s0, s0, s1 
+[0x60,0x09,0x20,0xee]
+
 # CHECK:        vmla.f16        s1, s2, s0
 [0x00,0x09,0x41,0xee]
 

diff  --git a/llvm/test/MC/Disassembler/ARM/fullfp16-thumb.txt b/llvm/test/MC/Disassembler/ARM/fullfp16-thumb.txt
index 4511720514363..c7d440631ee40 100644
--- a/llvm/test/MC/Disassembler/ARM/fullfp16-thumb.txt
+++ b/llvm/test/MC/Disassembler/ARM/fullfp16-thumb.txt
@@ -15,6 +15,9 @@
 # CHECK:        vnmul.f16       s0, s1, s0
 [0x20,0xee,0xc0,0x09]
 
+# CHECK:        vnmul.f16       s0, s0, s1 
+[0x20,0xee,0x60,0x09]
+
 # CHECK:        vmla.f16        s1, s2, s0
 [0x41,0xee,0x00,0x09]