[PATCH] D141602: [TTI][AArch64] Cost model insertelement and indexed LD1 instructions

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Do you have any performance results?

You are wanting to increase the cost? I had actually tried to do the opposite a little while ago, as there are some routines that would benefit from doing single lane load/inserts, so that the rest of the routine could vectorize nicely. It is one instruction after all, but I couldn't justify it in general because of the high cost.
The cost these routines measure reciprocal throughput by default, not latency. The operations seem to take two pipelines though, so a high cost would not be unreasonable.


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