[PATCH] D141657: [X86] Prefer fpext(splat(X)) to splat(fpext(x)).

[Freddy, Ye via Phabricator via llvm-commits]

FreddyYe created this revision.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141657

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/test/CodeGen/X86/prefer-fpext-splat.ll


Index: llvm/test/CodeGen/X86/prefer-fpext-splat.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/X86/prefer-fpext-splat.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f,+avx512vl | FileCheck %s
+
+ at f = global float 0.000000e+00, align 4
+
+define <4 x double> @prefer() {
+; CHECK-LABEL: prefer:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movq f at GOTPCREL(%rip), %rax
+; CHECK-NEXT:    vcvtps2pd (%rax){1to4}, %ymm0
+; CHECK-NEXT:    retq
+entry:
+  %0 = load float, float* @f, align 4
+  %vecinit.i = insertelement <4 x float> undef, float %0, i64 0
+  %vecinit3.i = shufflevector <4 x float> %vecinit.i, <4 x float> poison, <4 x i32> zeroinitializer
+  %conv.i = fpext <4 x float> %vecinit3.i to <4 x double>
+  ret <4 x double> %conv.i
+}
+
Index: llvm/lib/Target/X86/X86ISelLowering.h
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.h
+++ llvm/lib/Target/X86/X86ISelLowering.h
@@ -1091,6 +1091,8 @@
         unsigned OldShiftOpcode, unsigned NewShiftOpcode,
         SelectionDAG &DAG) const override;
 
+    bool preferScalarizeSplat(unsigned Opc) const override;
+
     bool shouldFoldConstantShiftPairToMask(const SDNode *N,
                                            CombineLevel Level) const override;
 
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -6012,6 +6012,12 @@
   return NewShiftOpcode == ISD::SHL;
 }
 
+bool X86TargetLowering::preferScalarizeSplat(unsigned Opc) const {
+  if (Opc == ISD::FP_EXTEND)
+    return false;
+  return true;
+}
+
 bool X86TargetLowering::shouldFoldConstantShiftPairToMask(
     const SDNode *N, CombineLevel Level) const {
   assert(((N->getOpcode() == ISD::SHL &&


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