[llvm] 3718848 - AMDGPU/GlobalISel: Make regbankselect of implicit_def consistent with constants
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 12 19:52:16 PST 2023
Author: Matt Arsenault
Date: 2023-01-12T22:52:09-05:00
New Revision: 371884865393141b0216b6479260b6feef5915ee
URL: https://github.com/llvm/llvm-project/commit/371884865393141b0216b6479260b6feef5915ee
DIFF: https://github.com/llvm/llvm-project/commit/371884865393141b0216b6479260b6feef5915ee.diff
LOG: AMDGPU/GlobalISel: Make regbankselect of implicit_def consistent with constants
Added:
Modified:
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
index bffbb3d78464..b21cd788dcf5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
@@ -459,7 +459,8 @@ AMDGPURegisterBankInfo::getInstrAlternativeMappings(
InstructionMappings AltMappings;
switch (MI.getOpcode()) {
- case TargetOpcode::G_CONSTANT: {
+ case TargetOpcode::G_CONSTANT:
+ case TargetOpcode::G_IMPLICIT_DEF: {
unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
if (Size == 1) {
static const OpRegBankEntry<1> Table[3] = {
@@ -2117,7 +2118,8 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
unsigned Opc = MI.getOpcode();
MachineRegisterInfo &MRI = OpdMapper.getMRI();
switch (Opc) {
- case AMDGPU::G_CONSTANT: {
+ case AMDGPU::G_CONSTANT:
+ case AMDGPU::G_IMPLICIT_DEF: {
Register DstReg = MI.getOperand(0).getReg();
LLT DstTy = MRI.getType(DstReg);
if (DstTy != LLT::scalar(1))
@@ -2138,9 +2140,11 @@ void AMDGPURegisterBankInfo::applyMappingImpl(
LLVMContext &Ctx = B.getMF().getFunction().getContext();
MI.getOperand(0).setReg(NewDstReg);
- uint64_t ConstVal = MI.getOperand(1).getCImm()->getZExtValue();
- MI.getOperand(1).setCImm(
- ConstantInt::get(IntegerType::getInt32Ty(Ctx), ConstVal));
+ if (Opc != AMDGPU::G_IMPLICIT_DEF) {
+ uint64_t ConstVal = MI.getOperand(1).getCImm()->getZExtValue();
+ MI.getOperand(1).setCImm(
+ ConstantInt::get(IntegerType::getInt32Ty(Ctx), ConstVal));
+ }
MRI.setRegBank(NewDstReg, *DstBank);
B.buildTrunc(DefRegs[0], NewDstReg);
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
index acfe7fb3de9d..12642b71a986 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
@@ -1,6 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck %s
-# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-fast -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,FAST %s
+# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -regbankselect-greedy -verify-machineinstrs -o - %s | FileCheck -check-prefixes=CHECK,GREEDY %s
---
name: test_implicit_def_s32_vgpr_use
@@ -132,8 +132,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr8
; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr9
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[DEF]](s1)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[DEF]](s32)
+ ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[TRUNC]](s1)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[ZEXT]](s32), [[COPY]], [[COPY1]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
%0:_(s32) = COPY $sgpr8
@@ -155,8 +156,9 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[DEF]](s1)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[DEF]](s32)
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[COPY]], [[COPY1]]
; CHECK-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
%0:_(s32) = COPY $vgpr0
@@ -173,15 +175,24 @@ legalized: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1
- ; CHECK-LABEL: name: test_implicit_def_s1_explicit_vcc_use_0
- ; CHECK: liveins: $vgpr0, $vgpr1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[DEF]](s1)
- ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[COPY]], [[COPY1]]
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
+ ; FAST-LABEL: name: test_implicit_def_s1_explicit_vcc_use_0
+ ; FAST: liveins: $vgpr0, $vgpr1
+ ; FAST-NEXT: {{ $}}
+ ; FAST-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; FAST-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; FAST-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+ ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[DEF]](s32)
+ ; FAST-NEXT: [[COPY2:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; FAST-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[COPY2]](s1), [[COPY]], [[COPY1]]
+ ; FAST-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
+ ; GREEDY-LABEL: name: test_implicit_def_s1_explicit_vcc_use_0
+ ; GREEDY: liveins: $vgpr0, $vgpr1
+ ; GREEDY-NEXT: {{ $}}
+ ; GREEDY-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
+ ; GREEDY-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
+ ; GREEDY-NEXT: [[DEF:%[0-9]+]]:vcc(s1) = G_IMPLICIT_DEF
+ ; GREEDY-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[DEF]](s1), [[COPY]], [[COPY1]]
+ ; GREEDY-NEXT: S_ENDPGM 0, implicit [[SELECT]](s32)
%0:_(s32) = COPY $vgpr0
%1:_(s32) = COPY $vgpr1
%2:vcc(s1) = G_IMPLICIT_DEF
@@ -195,10 +206,14 @@ name: test_implicit_def_s1_explicit_vcc_use_1
legalized: true
body: |
bb.0:
- ; CHECK-LABEL: name: test_implicit_def_s1_explicit_vcc_use_1
- ; CHECK: [[DEF:%[0-9]+]]:sgpr(s1) = G_IMPLICIT_DEF
- ; CHECK-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[DEF]](s1)
- ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY]](s1)
+ ; FAST-LABEL: name: test_implicit_def_s1_explicit_vcc_use_1
+ ; FAST: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF
+ ; FAST-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[DEF]](s32)
+ ; FAST-NEXT: [[COPY:%[0-9]+]]:vcc(s1) = COPY [[TRUNC]](s1)
+ ; FAST-NEXT: S_ENDPGM 0, implicit [[COPY]](s1)
+ ; GREEDY-LABEL: name: test_implicit_def_s1_explicit_vcc_use_1
+ ; GREEDY: [[DEF:%[0-9]+]]:vcc(s1) = G_IMPLICIT_DEF
+ ; GREEDY-NEXT: S_ENDPGM 0, implicit [[DEF]](s1)
%2:vcc(s1) = G_IMPLICIT_DEF
S_ENDPGM 0, implicit %2
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