[PATCH] D66571: [X86] Add a DAG combine to turn vector (and (srl X, ((1 << C1) - 1)), C2) into (srl (shl (X, C3), C4)) to save a constant pool for the AND mask

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri resigned from this revision.
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This review seems to be stuck/dead, consider abandoning if no longer relevant.


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https://reviews.llvm.org/D66571