[llvm] d3dcc0a - [AArch64] Add IfConv test with loads with invariant ops as conditions.
Florian Hahn via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 12 14:39:00 PST 2023
Author: Florian Hahn
Date: 2023-01-12T22:38:39Z
New Revision: d3dcc0affb75eb6dfeabe5969ca5c459bd5a8df8
URL: https://github.com/llvm/llvm-project/commit/d3dcc0affb75eb6dfeabe5969ca5c459bd5a8df8
DIFF: https://github.com/llvm/llvm-project/commit/d3dcc0affb75eb6dfeabe5969ca5c459bd5a8df8.diff
LOG: [AArch64] Add IfConv test with loads with invariant ops as conditions.
Add EarlyIfConversion tests for AArch64 where the condition is a load
with invariant operands. A follow-up patch will propose a heuristic to
consider such conditions predictable.
Added:
llvm/test/CodeGen/AArch64/early-ifcvt-likely-predictable.mir
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/early-ifcvt-likely-predictable.mir b/llvm/test/CodeGen/AArch64/early-ifcvt-likely-predictable.mir
new file mode 100644
index 0000000000000..2c3670ab236b5
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/early-ifcvt-likely-predictable.mir
@@ -0,0 +1,227 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=arm64-apple-ios -mcpu=apple-m1 -run-pass=early-ifcvt -o - %s | FileCheck %s
+
+--- |
+ define void @test_cond_is_load_with_invariant_ops() {
+ entry:
+ ret void
+ }
+
+ define void @test_cond_is_load_with_invariant_ops2() {
+ entry:
+ ret void
+ }
+
+ define void @test_cond_is_load_with_varying_ops() {
+ entry:
+ ret void
+ }
+...
+---
+name: test_cond_is_load_with_invariant_ops
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_cond_is_load_with_invariant_ops
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x0, $x1, $w2, $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32common = COPY $w2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32common = LDRBBui [[COPY3]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY [[COPY4]]
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 4080, 12, implicit-def $nzcv
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16711680
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32common = CSELWr [[COPY1]], killed [[MOVi32imm]], 11, implicit $nzcv
+ ; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[CSELWr]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr32 = COPY $wzr
+ ; CHECK-NEXT: [[CSELWr1:%[0-9]+]]:gpr32 = CSELWr [[CSELWr]], [[COPY6]], 12, implicit $nzcv
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32 = COPY [[CSELWr1]]
+ ; CHECK-NEXT: [[SUBSWri2:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr2:%[0-9]+]]:gpr32 = CSELWr [[COPY1]], [[COPY6]], 12, implicit $nzcv
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr32 = COPY [[CSELWr2]]
+ ; CHECK-NEXT: $wzr = SUBSWri [[LDRBBui]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr3:%[0-9]+]]:gpr32 = CSELWr [[COPY5]], [[COPY7]], 0, implicit $nzcv
+ ; CHECK-NEXT: $wzr = SUBSWri [[LDRBBui]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr4:%[0-9]+]]:gpr32 = CSELWr [[COPY5]], [[COPY8]], 0, implicit $nzcv
+ ; CHECK-NEXT: STRBBui [[CSELWr4]], [[COPY2]], 0 :: (store (s8))
+ ; CHECK-NEXT: STRBBui [[CSELWr3]], [[COPY]], 0 :: (store (s8))
+ ; CHECK-NEXT: B %bb.1
+ bb.0:
+ liveins: $x0, $x1, $w2, $x3
+
+ %20:gpr64common = COPY $x3
+ %6:gpr32common = COPY $w2
+ %5:gpr64common = COPY $x1
+ %4:gpr64common = COPY $x0
+
+ bb.1:
+ successors: %bb.3(0x30000000), %bb.2(0x50000000)
+
+ %9:gpr32 = LDRBBui %4, 0 :: (load (s8))
+ %10:gpr32all = COPY $wzr
+ %8:gpr32all = COPY %10
+ CBZW killed %9, %bb.3
+ B %bb.2
+
+ bb.2:
+ %11:gpr32 = SUBSWri %6, 4080, 12, implicit-def $nzcv
+ %12:gpr32 = MOVi32imm 16711680
+ %13:gpr32common = CSELWr %6, killed %12, 11, implicit $nzcv
+ %14:gpr32 = SUBSWri %13, 0, 0, implicit-def $nzcv
+ %15:gpr32 = COPY $wzr
+ %16:gpr32 = CSELWr %13, %15, 12, implicit $nzcv
+ %0:gpr32all = COPY %16
+ %17:gpr32 = SUBSWri %6, 0, 0, implicit-def $nzcv
+ %18:gpr32 = CSELWr %6, %15, 12, implicit $nzcv
+ %1:gpr32all = COPY %18
+
+ bb.3:
+ %2:gpr32 = PHI %8, %bb.1, %0, %bb.2
+ %3:gpr32 = PHI %8, %bb.1, %1, %bb.2
+ STRBBui %3, %5, 0 :: (store (s8))
+ STRBBui %2, %20, 0 :: (store (s8))
+ B %bb.1
+
+...
+---
+name: test_cond_is_load_with_invariant_ops2
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_cond_is_load_with_invariant_ops2
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x0, $x1, $w2, $x3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x3
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32common = COPY $w2
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32common = LDRBBui [[COPY3]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32all = COPY $wzr
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32all = COPY [[COPY4]]
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr32 = COPY [[LDRBBui]]
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 4080, 12, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32 = COPY [[SUBSWri]]
+ ; CHECK-NEXT: $wzr = SUBSWri [[LDRBBui]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32 = CSELWr [[COPY6]], [[COPY7]], 0, implicit $nzcv
+ ; CHECK-NEXT: STRBBui [[CSELWr]], [[COPY]], 0 :: (store (s8))
+ ; CHECK-NEXT: B %bb.1
+ bb.0:
+ liveins: $x0, $x1, $w2, $x3
+
+ %20:gpr64common = COPY $x3
+ %6:gpr32common = COPY $w2
+ %5:gpr64common = COPY $x1
+ %4:gpr64common = COPY $x0
+
+ bb.1:
+ successors: %bb.3(0x30000000), %bb.2(0x50000000)
+
+ %9:gpr32 = LDRBBui %4, 0 :: (load (s8))
+ %10:gpr32all = COPY $wzr
+ %8:gpr32all = COPY %10
+ %21:gpr32all = COPY %9
+ CBZW killed %9, %bb.3
+ B %bb.2
+
+ bb.2:
+ %11:gpr32 = SUBSWri %6, 4080, 12, implicit-def $nzcv
+ %0:gpr32all = COPY %11
+
+ bb.3:
+ %2:gpr32 = PHI %21, %bb.1, %0, %bb.2
+ STRBBui %2, %20, 0 :: (store (s8))
+ B %bb.1
+
+...
+---
+name: test_cond_is_load_with_varying_ops
+alignment: 4
+tracksRegLiveness: true
+body: |
+ ; CHECK-LABEL: name: test_cond_is_load_with_varying_ops
+ ; CHECK: bb.0:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: liveins: $x0, $x1, $w2
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32common = COPY $w2
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: bb.1:
+ ; CHECK-NEXT: successors: %bb.1(0x80000000)
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr64sp = PHI [[COPY2]], %bb.0, %4, %bb.1
+ ; CHECK-NEXT: [[LDRBBui:%[0-9]+]]:gpr32common = LDRBBui [[PHI]], 0 :: (load (s8))
+ ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr32all = COPY $wzr
+ ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr32 = COPY [[COPY3]]
+ ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 4080, 12, implicit-def $nzcv
+ ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 16711680
+ ; CHECK-NEXT: [[CSELWr:%[0-9]+]]:gpr32common = CSELWr [[COPY]], killed [[MOVi32imm]], 11, implicit $nzcv
+ ; CHECK-NEXT: [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[CSELWr]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr32 = COPY $wzr
+ ; CHECK-NEXT: [[CSELWr1:%[0-9]+]]:gpr32 = CSELWr [[CSELWr]], [[COPY5]], 12, implicit $nzcv
+ ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr32 = COPY [[CSELWr1]]
+ ; CHECK-NEXT: [[SUBSWri2:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr2:%[0-9]+]]:gpr32 = CSELWr [[COPY]], [[COPY5]], 12, implicit $nzcv
+ ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr32 = COPY [[CSELWr2]]
+ ; CHECK-NEXT: $wzr = SUBSWri [[LDRBBui]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr3:%[0-9]+]]:gpr32 = CSELWr [[COPY4]], [[COPY6]], 0, implicit $nzcv
+ ; CHECK-NEXT: $wzr = SUBSWri [[LDRBBui]], 0, 0, implicit-def $nzcv
+ ; CHECK-NEXT: [[CSELWr4:%[0-9]+]]:gpr32 = CSELWr [[COPY4]], [[COPY7]], 0, implicit $nzcv
+ ; CHECK-NEXT: STRBBui [[CSELWr4]], [[COPY1]], 0 :: (store (s8))
+ ; CHECK-NEXT: early-clobber %20:gpr64sp = STRBBpost [[CSELWr3]], [[PHI]], 1 :: (store (s8))
+ ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr64all = COPY %20
+ ; CHECK-NEXT: B %bb.1
+ bb.0:
+ liveins: $x0, $x1, $w2
+
+ %8:gpr32common = COPY $w2
+ %7:gpr64common = COPY $x1
+ %6:gpr64 = COPY $x0
+
+ bb.1:
+ successors: %bb.3(0x30000000), %bb.2(0x50000000)
+
+ %0:gpr64sp = PHI %6, %bb.0, %5, %bb.3
+ %11:gpr32 = LDRBBui %0, 0 :: (load (s8))
+ %12:gpr32all = COPY $wzr
+ %10:gpr32all = COPY %12
+ CBZW killed %11, %bb.3
+ B %bb.2
+
+ bb.2:
+ %13:gpr32 = SUBSWri %8, 4080, 12, implicit-def $nzcv
+ %14:gpr32 = MOVi32imm 16711680
+ %15:gpr32common = CSELWr %8, killed %14, 11, implicit $nzcv
+ %16:gpr32 = SUBSWri %15, 0, 0, implicit-def $nzcv
+ %17:gpr32 = COPY $wzr
+ %18:gpr32 = CSELWr %15, %17, 12, implicit $nzcv
+ %1:gpr32all = COPY %18
+ %19:gpr32 = SUBSWri %8, 0, 0, implicit-def $nzcv
+ %20:gpr32 = CSELWr %8, %17, 12, implicit $nzcv
+ %2:gpr32all = COPY %20
+
+ bb.3:
+ %3:gpr32 = PHI %10, %bb.1, %1, %bb.2
+ %4:gpr32 = PHI %10, %bb.1, %2, %bb.2
+ STRBBui %4, %7, 0 :: (store (s8))
+ early-clobber %21:gpr64sp = STRBBpost %3, %0, 1 :: (store (s8))
+ %5:gpr64all = COPY %21
+ B %bb.1
+
+...
More information about the llvm-commits
mailing list