[PATCH] D141464: [X86]: Match (xor TSize - 1, ctlz) to `bsr` instead of `lzcnt` + `xor`

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n marked an inline comment as done.
goldstein.w.n added inline comments.


================
Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:51923
+
+  Op = DAG.getNode(X86ISD::BSR, DL, OpVT, Op);
+  if (VT == MVT::i8) {
----------------
craig.topper wrote:
> This needs to be
> 
> ```
>   SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);                                  
>   Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
> ```
> 
> We have X86ISD::BSR plumbed to also returns flags so it has a second i32 out put for the flags.
> This needs to be
> 
> ```
>   SDVTList VTs = DAG.getVTList(OpVT, MVT::i32);                                  
>   Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op);
> ```
> 
> We have X86ISD::BSR plumbed to also returns flags so it has a second i32 out put for the flags.




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https://reviews.llvm.org/D141464