[PATCH] D141289: [MIScheduler] Print top/down cycle in the SUnit dump.
Francesco Petrogalli via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 12 06:29:36 PST 2023
fpetrogalli updated this revision to Diff 488636.
fpetrogalli added a comment.
I have specified -mcpu in the test and the resulting values printed in the SUnit dump.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D141289/new/
https://reviews.llvm.org/D141289
Files:
llvm/lib/CodeGen/ScheduleDAG.cpp
llvm/test/CodeGen/AArch64/sched-print-cycle.mir
Index: llvm/test/CodeGen/AArch64/sched-print-cycle.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sched-print-cycle.mir
@@ -0,0 +1,23 @@
+# RUN: llc -mcpu=apple-m1 -sched-print-cycles=true \
+# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s
+
+# RUN: llc -mcpu=apple-m1 -sched-print-cycles=false \
+# RUN: -run-pass=machine-scheduler -debug-only=machine-scheduler -o - %s 2>&1 | FileCheck %s --check-prefix=NOCYCLES
+
+# REQUIRES: asserts
+---
+name: mul_mul
+tracksRegLiveness: true
+body: |
+ bb.0:
+ liveins: $x0
+ $x1 = ADDXrr $x0, $x0
+ $x2 = ADDXrr $x1, $x1
+
+# CHECK-LABEL: *** Final schedule for %bb.0 ***
+# CHECK: SU(0 0 0): $x1 = ADDXrr $x0, $x0
+# CHECK: SU(1 0 0): $x2 = ADDXrr $x1, $x1
+
+# NOCYCLES-LABEL: *** Final schedule for %bb.0 ***
+# NOCYCLES: SU(0): $x1 = ADDXrr $x0, $x0
+# NOCYCLES: SU(1): $x2 = ADDXrr $x1, $x1
Index: llvm/lib/CodeGen/ScheduleDAG.cpp
===================================================================
--- llvm/lib/CodeGen/ScheduleDAG.cpp
+++ llvm/lib/CodeGen/ScheduleDAG.cpp
@@ -46,6 +46,10 @@
static cl::opt<bool> StressSchedOpt(
"stress-sched", cl::Hidden, cl::init(false),
cl::desc("Stress test instruction scheduling"));
+
+static cl::opt<bool> SchedPrintCycles(
+ "sched-print-cycles", cl::Hidden, cl::init(false),
+ cl::desc("Report top/bottom cycles when dumping SUnit instances"));
#endif
void SchedulingPriorityQueue::anchor() {}
@@ -356,8 +360,12 @@
dbgs() << "EntrySU";
else if (&SU == &ExitSU)
dbgs() << "ExitSU";
- else
- dbgs() << "SU(" << SU.NodeNum << ")";
+ else {
+ dbgs() << "SU(" << SU.NodeNum;
+ if (SchedPrintCycles)
+ dbgs() << " " << SU.TopReadyCycle << " " << SU.BotReadyCycle;
+ dbgs()<< ")";
+ }
}
LLVM_DUMP_METHOD void ScheduleDAG::dumpNodeAll(const SUnit &SU) const {
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