[PATCH] D141607: [RISCV] Optimize (brcond (seteq (and X, (1 << C)-1), 0))

[Liao Chunyu via Phabricator via llvm-commits]

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Inspired by gcc's assembly: https://godbolt.org/z/54hbzsGYn, while referring to D130203 <https://reviews.llvm.org/D130203>

Replace AND+IMM{32,64} with a slli.

But gcc does not handle 0xffff and 0xffffffff, which also seem to be optimizable.

The testcases copies all the bits in D130203 <https://reviews.llvm.org/D130203> and adds 16, 32, and 64 bits.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141607

Files:
  llvm/test/CodeGen/RISCV/bittest.ll

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