[PATCH] D141469: [AArch64][SVE] Add more intrinsics in 'isZeroingInactiveLanes'.

[dewen via Phabricator via llvm-commits]

dewen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:305
+    case Intrinsic::aarch64_sve_uzp2:
+    case Intrinsic::aarch64_sve_sel:
+    case Intrinsic::aarch64_sve_orr_z:
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dewen wrote:
> sdesmalen wrote:
> > Predicate select is slightly different, since there is only a full-vector predicate select (operating on svbool_t), so there are no inactive lanes. It might be worth to point that out in a comment.
> > 
> > Can you please add a test for this case? it seems to be missing.
> Okay, thank you. @sdesmalen
I have updated. Please review. @sdesmalen


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141469/new/

https://reviews.llvm.org/D141469