[PATCH] D141603: [AArch64][SME] Allow predicate-as-counter operands for psel

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: CarolineConcatto, MattDevereau.
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The specification says:

  For programmer convenience, an assembler must also accept
  predicate-as-counter register names for the destination predicate
  register and the first source predicate register


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141603

Files:
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/SMEInstrFormats.td
  llvm/test/MC/AArch64/SME/psel.s


Index: llvm/test/MC/AArch64/SME/psel.s
===================================================================
--- llvm/test/MC/AArch64/SME/psel.s
+++ llvm/test/MC/AArch64/SME/psel.s
@@ -119,3 +119,30 @@
 // CHECK-ENCODING: [0xef,0x7d,0xe3,0x25]
 // CHECK-ERROR: instruction requires: sme
 // CHECK-UNKNOWN: 25e37def <unknown>
+
+// --------------------------------------------------------------------------//
+// Also support with predicate-as-counter
+
+psel    pn15, pn15, p15.b[w15, 15]
+// CHECK-INST: psel    p15, p15, p15.b[w15, 15]
+// CHECK-ENCODING: [0xef,0x7d,0xff,0x25]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25ff7def <unknown>
+
+psel    pn15, pn15, p15.h[w15, 7]
+// CHECK-INST: psel    p15, p15, p15.h[w15, 7]
+// CHECK-ENCODING: [0xef,0x7d,0xfb,0x25]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25fb7def <unknown>
+
+psel    pn15, pn15, p15.s[w15, 3]
+// CHECK-INST: psel    p15, p15, p15.s[w15, 3]
+// CHECK-ENCODING: [0xef,0x7d,0xf3,0x25]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25f37def <unknown>
+
+psel    pn15, pn15, p15.d[w15, 1]
+// CHECK-INST: psel    p15, p15, p15.d[w15, 1]
+// CHECK-ENCODING: [0xef,0x7d,0xe3,0x25]
+// CHECK-ERROR: instruction requires: sme
+// CHECK-UNKNOWN: 25e37def <unknown>
Index: llvm/lib/Target/AArch64/SMEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -1170,6 +1170,19 @@
     let Inst{20-18} = 0b000;
   }
 
+  def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
+                  (!cast<Instruction>(NAME # _B) PNRAny:$Pd,
+                      PNRAny:$Pn, PPR8:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_15:$imm), 0>;
+  def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
+                  (!cast<Instruction>(NAME # _H) PNRAny:$Pd,
+                      PNRAny:$Pn, PPR16:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_7:$imm), 0>;
+  def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
+                  (!cast<Instruction>(NAME # _S) PNRAny:$Pd,
+                      PNRAny:$Pn, PPR32:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_3:$imm), 0>;
+  def : InstAlias<asm # "\t$Pd, $Pn, $Pm[$Rv, $imm]",
+                  (!cast<Instruction>(NAME # _D) PNRAny:$Pd,
+                      PNRAny:$Pn, PPR64:$Pm, MatrixIndexGPR32Op12_15:$Rv, sme_elm_idx0_1:$imm), 0>;
+
   def : Pat<(nxv16i1 (op (nxv16i1 PPRAny:$Pn), (nxv16i1 PPRAny:$Pm),
              MatrixIndexGPR32Op12_15:$idx)),
             (!cast<Instruction>(NAME # _B) $Pn, $Pm, $idx, 0)>;
Index: llvm/lib/Target/AArch64/AArch64RegisterInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -941,11 +941,13 @@
   let PrintMethod = "printPredicateAsCounter<" # EltSize # ">";
 }
 
+def PNRAsmOpAny: PNRAsmOperand<"PNPredicateAny", "PPR", 0>;
 def PNRAsmOp8  : PNRAsmOperand<"PNPredicateB", "PPR", 8>;
 def PNRAsmOp16 : PNRAsmOperand<"PNPredicateH", "PPR", 16>;
 def PNRAsmOp32 : PNRAsmOperand<"PNPredicateS", "PPR", 32>;
 def PNRAsmOp64 : PNRAsmOperand<"PNPredicateD", "PPR", 64>;
 
+def PNRAny : PNRRegOp<"", PNRAsmOpAny, 0,  PPR>;
 def PNR8   : PNRRegOp<"b", PNRAsmOp8,  8,  PPR>;
 def PNR16  : PNRRegOp<"h", PNRAsmOp16, 16, PPR>;
 def PNR32  : PNRRegOp<"s", PNRAsmOp32, 32, PPR>;


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