[PATCH] D141601: [AArch64][SME2] MOVA tile-to-vector and vector-to-tile should not accept VG suffix

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: CarolineConcatto, MattDevereau.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a project: All.
sdesmalen requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141601

Files:
  llvm/lib/Target/AArch64/SMEInstrFormats.td
  llvm/test/MC/AArch64/SME2/mova-diagnostics.s


Index: llvm/test/MC/AArch64/SME2/mova-diagnostics.s
===================================================================
--- llvm/test/MC/AArch64/SME2/mova-diagnostics.s
+++ llvm/test/MC/AArch64/SME2/mova-diagnostics.s
@@ -71,3 +71,47 @@
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .h
 // CHECK-NEXT: mov {z0.h-z3.h}, za.d[w8, 0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+
+// --------------------------------------------------------------------------//
+// Tile-to-vector and vector-to-tile should not accept the VG suffix
+
+mov za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mov { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova za0h.b[w12, 0:1, vgx2], { z0.b, z1.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova { z0.b, z1.b }, za0h.b[w12, 0:1, vgx2]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova za0h.b[w12, 0:3, vgx4], { z0.b - z3.b }
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+mova { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: mova { z0.b - z3.b }, za0h.b[w12, 0:3, vgx4]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Index: llvm/lib/Target/AArch64/SMEInstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/SMEInstrFormats.td
+++ llvm/lib/Target/AArch64/SMEInstrFormats.td
@@ -2766,7 +2766,7 @@
                                            string mnemonic>
    : I<(outs tile_ty:$ZAd),
        (ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm, vector_ty:$Zn),
-       mnemonic, "\t$ZAd[$Rs, $imm, vgx2], $Zn",
+       mnemonic, "\t$ZAd[$Rs, $imm], $Zn",
        "", []>, Sched<[]> {
   bits<2> Rs;
   bits<4> Zn;
@@ -2927,7 +2927,7 @@
        (ins tile_ty:$_ZAd, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm,
             vector_ty:$Zn),
        mnemonic,
-       "\t$ZAd[$Rs, $imm, vgx4], $Zn",
+       "\t$ZAd[$Rs, $imm], $Zn",
        "", []>, Sched<[]> {
   bits<2> Rs;
   bits<3> Zn;
@@ -3248,7 +3248,7 @@
    : I<!if(op{1}, (outs vector_ty:$Zd, tile_ty:$_ZAn), (outs vector_ty:$Zd)),
        (ins tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm),
        mnemonic,
-       "\t$Zd, $ZAn[$Rs, $imm, vgx2]",
+       "\t$Zd, $ZAn[$Rs, $imm]",
        "", []>, Sched<[]> {
   bits<4> Zd;
   bits<2> Rs;
@@ -3445,7 +3445,7 @@
    : I<!if(op{4}, (outs vector_ty:$Zd, tile_ty:$_ZAn), (outs vector_ty:$Zd)),
        (ins tile_ty:$ZAn, MatrixIndexGPR32Op12_15:$Rs, index_ty:$imm),
        mnemonic,
-       "\t$Zd, $ZAn[$Rs, $imm, vgx4]",
+       "\t$Zd, $ZAn[$Rs, $imm]",
        "", []>, Sched<[]> {
   bits<3> Zd;
   bits<2> Rs;


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