[llvm] f460c66 - [AMDGPU] Simplify getNumFlatOffsetBits. NFC.
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 12 02:40:42 PST 2023
Author: Jay Foad
Date: 2023-01-12T10:40:36Z
New Revision: f460c6658107ba214edadcdac9aa0656c4c51505
URL: https://github.com/llvm/llvm-project/commit/f460c6658107ba214edadcdac9aa0656c4c51505
DIFF: https://github.com/llvm/llvm-project/commit/f460c6658107ba214edadcdac9aa0656c4c51505.diff
LOG: [AMDGPU] Simplify getNumFlatOffsetBits. NFC.
Previously we considered this field to be either N-bit unsigned or
N+1-bit signed, depending on the instruction. I think it's conceptually
simpler to say that the field is always N+1-bit signed, but some
instructions do not allow negative values.
Differential Revision: https://reviews.llvm.org/D140883
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 92d1ba23c5639..859761bd81ffe 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -4118,20 +4118,15 @@ bool AMDGPUAsmParser::validateFlatOffset(const MCInst &Inst,
// For FLAT segment the offset must be positive;
// MSB is ignored and forced to zero.
- if (TSFlags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch)) {
- unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI(), true);
- if (!isIntN(OffsetSize, Op.getImm())) {
- Error(getFlatOffsetLoc(Operands),
- Twine("expected a ") + Twine(OffsetSize) + "-bit signed offset");
- return false;
- }
- } else {
- unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI(), false);
- if (!isUIntN(OffsetSize, Op.getImm())) {
- Error(getFlatOffsetLoc(Operands),
- Twine("expected a ") + Twine(OffsetSize) + "-bit unsigned offset");
- return false;
- }
+ unsigned OffsetSize = AMDGPU::getNumFlatOffsetBits(getSTI());
+ bool AllowNegative =
+ TSFlags & (SIInstrFlags::FlatGlobal | SIInstrFlags::FlatScratch);
+ if (!isIntN(OffsetSize, Op.getImm()) || (!AllowNegative && Op.getImm() < 0)) {
+ Error(getFlatOffsetLoc(Operands),
+ Twine("expected a ") +
+ (AllowNegative ? Twine(OffsetSize) + "-bit signed offset"
+ : Twine(OffsetSize - 1) + "-bit unsigned offset"));
+ return false;
}
return true;
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 01c04c1acfb7f..03de65fcd72f9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -7939,18 +7939,18 @@ bool SIInstrInfo::isLegalFLATOffset(int64_t Offset, unsigned AddrSpace,
AddrSpace == AMDGPUAS::GLOBAL_ADDRESS))
return false;
- bool Signed = FlatVariant != SIInstrFlags::FLAT;
+ bool AllowNegative = FlatVariant != SIInstrFlags::FLAT;
if (ST.hasNegativeScratchOffsetBug() &&
FlatVariant == SIInstrFlags::FlatScratch)
- Signed = false;
+ AllowNegative = false;
if (ST.hasNegativeUnalignedScratchOffsetBug() &&
FlatVariant == SIInstrFlags::FlatScratch && Offset < 0 &&
(Offset % 4) != 0) {
return false;
}
- unsigned N = AMDGPU::getNumFlatOffsetBits(ST, Signed);
- return Signed ? isIntN(N, Offset) : isUIntN(N, Offset);
+ unsigned N = AMDGPU::getNumFlatOffsetBits(ST);
+ return isIntN(N, Offset) && (AllowNegative || Offset >= 0);
}
// See comment on SIInstrInfo::isLegalFLATOffset for what is legal and what not.
@@ -7959,15 +7959,15 @@ SIInstrInfo::splitFlatOffset(int64_t COffsetVal, unsigned AddrSpace,
uint64_t FlatVariant) const {
int64_t RemainderOffset = COffsetVal;
int64_t ImmField = 0;
- bool Signed = FlatVariant != SIInstrFlags::FLAT;
+ bool AllowNegative = FlatVariant != SIInstrFlags::FLAT;
if (ST.hasNegativeScratchOffsetBug() &&
FlatVariant == SIInstrFlags::FlatScratch)
- Signed = false;
+ AllowNegative = false;
- const unsigned NumBits = AMDGPU::getNumFlatOffsetBits(ST, Signed);
- if (Signed) {
+ const unsigned NumBits = AMDGPU::getNumFlatOffsetBits(ST) - 1;
+ if (AllowNegative) {
// Use signed division by a power of two to truncate towards 0.
- int64_t D = 1LL << (NumBits - 1);
+ int64_t D = 1LL << NumBits;
RemainderOffset = (COffsetVal / D) * D;
ImmField = COffsetVal - RemainderOffset;
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
index 54b72bf5a53b5..37b8d8125e69f 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -2502,12 +2502,12 @@ std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
: std::nullopt;
}
-unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed) {
+unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST) {
// Address offset is 12-bit signed for GFX10, 13-bit for GFX9 and GFX11+.
if (AMDGPU::isGFX10(ST))
- return Signed ? 12 : 11;
+ return 12;
- return Signed ? 13 : 12;
+ return 13;
}
// Given Imm, split it into the values to put into the SOffset and ImmOffset
diff --git a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
index ea5ecf69dfcfa..2022e0f0b251f 100644
--- a/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ b/llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -1265,9 +1265,10 @@ std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
/// For FLAT segment the offset must be positive;
/// MSB is ignored and forced to zero.
///
-/// \return The number of bits available for the offset field in flat
-/// instructions.
-unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST, bool Signed);
+/// \return The number of bits available for the signed offset field in flat
+/// instructions. Note that some forms of the instruction disallow negative
+/// offsets.
+unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST);
/// \returns true if this offset is small enough to fit in the SMRD
/// offset field. \p ByteOffset should be the offset in bytes and
More information about the llvm-commits
mailing list