[PATCH] D141469: [AArch64][SVE] Add more intrinsics in 'isZeroingInactiveLanes'.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added a subscriber: hassnaa-arm.
sdesmalen added a comment.

@hassnaa-arm  this patch seems to solve the same issue as you're trying to solve in D141397 <https://reviews.llvm.org/D141397>.



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:305
+    case Intrinsic::aarch64_sve_uzp2:
+    case Intrinsic::aarch64_sve_sel:
+    case Intrinsic::aarch64_sve_orr_z:
----------------
Predicate select is slightly different, since there is only a full-vector predicate select (operating on svbool_t), so there are no inactive lanes. It might be worth to point that out in a comment.

Can you please add a test for this case? it seems to be missing.


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Comment at: llvm/test/CodeGen/AArch64/sve2-intrinsics-reinterpret.ll:384
+  %1 = call <vscale x 2 x i1> @llvm.aarch64.sve.trn1.nxv2i1(<vscale x 2 x i1> %a,
+                                                              <vscale x 2 x i1> %b)
+  %out = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %1)
----------------
nit: odd indentation


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  https://reviews.llvm.org/D141469/new/

https://reviews.llvm.org/D141469