[PATCH] D141565: [RISCV][CodeGen] Account for LMUL from VS2 for Vector Reduction Instructions

[Monk Chiang via Phabricator via llvm-commits]

monkchiang created this revision.
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The Reduction instruction destination register LMUL is 1. But the source
register(vs2) has different LMUL(MF8 to M8). It's beneficial to know how
many registers are working on reduction instructions.
This patch creates separate SchedWrite for each relevant LMUL that from VS2.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141565

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

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