[PATCH] D141485: [X86] Add schedule module for SapphireRapids

Wed Jan 11 17:01:13 PST 2023

LuoYuanke added a comment.

In D141485#4043529 <https://reviews.llvm.org/D141485#4043529>, @RKSimon wrote:

> @HaohaiWen We don't currently have llvm-mca test coverage for the amx ISAs, I'll see if I can get that added at some point soon - have you noticed any other ISAs we're still missing please?

I can't find the latency and throughput of AMX instructions from https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html. It seems it is not disclosed yet. The avx512fp16 is a big ISA introduced in SPR, but we can use the same schedule model with float32 instructions. The TTI information may be added for avx512fp16.

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https://reviews.llvm.org/D141485