[PATCH] D112466: [NVPTX] Drop memory references of LDG/LDU

[Andrew Savonichev via Phabricator via llvm-commits]

asavonic updated this revision to Diff 488280.
asavonic added a comment.

- Rebased


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D112466/new/

https://reviews.llvm.org/D112466

Files:
  llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
  llvm/test/CodeGen/NVPTX/bug26185-2.ll
  llvm/test/CodeGen/NVPTX/bug26185.ll
  llvm/test/CodeGen/NVPTX/ldg-invariant.ll
  llvm/test/CodeGen/NVPTX/ldu-i8.ll
  llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
  llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
  llvm/test/CodeGen/NVPTX/read-global-variable-constant.ll


Index: llvm/test/CodeGen/NVPTX/read-global-variable-constant.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/read-global-variable-constant.ll
+++ llvm/test/CodeGen/NVPTX/read-global-variable-constant.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_35 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_35 -verify-machineinstrs | FileCheck %s
 ; RUN: %if ptxas %{ llc < %s -march=nvptx -mcpu=sm_35 | %ptxas-verify -arch=sm_35 %}
 
 ; Check load from constant global variables.  These loads should be
Index: llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
+++ llvm/test/CodeGen/NVPTX/load-with-non-coherent-cache.ll
@@ -1,5 +1,5 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 | FileCheck -check-prefix=SM20 %s
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck -check-prefix=SM35 %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_20 -verify-machineinstrs | FileCheck -check-prefix=SM20 %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 -verify-machineinstrs | FileCheck -check-prefix=SM35 %s
 ; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_20 | %ptxas-verify %}
 ; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_35 | %ptxas-verify -arch=sm_35 %}
 
Index: llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
+++ llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 ; RUN: %if ptxas %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Index: llvm/test/CodeGen/NVPTX/ldu-i8.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/ldu-i8.ll
+++ llvm/test/CodeGen/NVPTX/ldu-i8.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 ; RUN: %if ptxas %{ llc < %s -march=nvptx -mcpu=sm_20 | %ptxas-verify %}
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Index: llvm/test/CodeGen/NVPTX/ldg-invariant.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/ldg-invariant.ll
+++ llvm/test/CodeGen/NVPTX/ldg-invariant.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 | FileCheck %s
+; RUN: llc < %s -march=nvptx64 -mcpu=sm_35 -verify-machineinstrs | FileCheck %s
 ; RUN: %if ptxas %{ llc < %s -march=nvptx64 -mcpu=sm_35 | %ptxas-verify -arch=sm_35 %}
 
 ; Check that invariant loads from the global addrspace are lowered to
Index: llvm/test/CodeGen/NVPTX/bug26185.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/bug26185.ll
+++ llvm/test/CodeGen/NVPTX/bug26185.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_35 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_35 -verify-machineinstrs | FileCheck %s
 ; RUN: %if ptxas %{ llc < %s -march=nvptx -mcpu=sm_35 | %ptxas-verify -arch=sm_35 %}
 
 ; Verify that we correctly emit code for i8 ldg/ldu. We do not expose 8-bit
Index: llvm/test/CodeGen/NVPTX/bug26185-2.ll
===================================================================
--- llvm/test/CodeGen/NVPTX/bug26185-2.ll
+++ llvm/test/CodeGen/NVPTX/bug26185-2.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_35 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_35 -verify-machineinstrs | FileCheck %s
 ; RUN: %if ptxas %{ llc < %s -march=nvptx -mcpu=sm_35 | %ptxas-verify -arch=sm_35 %}
 
 ; Verify that we correctly emit code for extending ldg/ldu. We do not expose
Index: llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -1671,9 +1671,6 @@
     LD = CurDAG->getMachineNode(*Opcode, DL, InstVTList, Ops);
   }
 
-  MachineMemOperand *MemRef = Mem->getMemOperand();
-  CurDAG->setNodeMemRefs(cast<MachineSDNode>(LD), {MemRef});
-
   // For automatic generation of LDG (through SelectLoad[Vector], not the
   // intrinsics), we may have an extending load like:
   //


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