[llvm] e7341b5 - [RISCV] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-01-11T10:07:48-08:00
New Revision: e7341b51c2b0411a743eb34f732704ff7eb7279d

URL: https://github.com/llvm/llvm-project/commit/e7341b51c2b0411a743eb34f732704ff7eb7279d
DIFF: https://github.com/llvm/llvm-project/commit/e7341b51c2b0411a743eb34f732704ff7eb7279d.diff

LOG: [RISCV] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC

Use isPhysical/isVirtual methods.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 072fb4820f2c..5fad88da40e4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1092,8 +1092,7 @@ static MachineInstr *canFoldAsPredicatedOp(Register Reg,
     if (MO.isDef())
       return nullptr;
     // Allow constant physregs.
-    if (Register::isPhysicalRegister(MO.getReg()) &&
-        !MRI.isConstantPhysReg(MO.getReg()))
+    if (MO.getReg().isPhysical() && !MRI.isConstantPhysReg(MO.getReg()))
       return nullptr;
   }
   bool DontMoveAcrossStores = true;
@@ -1437,7 +1436,7 @@ RISCVInstrInfo::getInverseOpcode(unsigned Opcode) const {
 static bool canCombineFPFusedMultiply(const MachineInstr &Root,
                                       const MachineOperand &MO,
                                       bool DoRegPressureReduce) {
-  if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
+  if (!MO.isReg() || !MO.getReg().isVirtual())
     return false;
   const MachineRegisterInfo &MRI = Root.getMF()->getRegInfo();
   MachineInstr *MI = MRI.getVRegDef(MO.getReg());

diff  --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index f400628f93d4..927845aa23d1 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -706,8 +706,7 @@ bool RISCVRegisterInfo::getRegAllocationHints(
   auto tryAddHint = [&](const MachineOperand &VRRegMO, const MachineOperand &MO,
                         bool NeedGPRC) -> void {
     Register Reg = MO.getReg();
-    Register PhysReg =
-        Register::isPhysicalRegister(Reg) ? Reg : Register(VRM->getPhys(Reg));
+    Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
     if (PhysReg && (!NeedGPRC || RISCV::GPRCRegClass.contains(PhysReg))) {
       assert(!MO.getSubReg() && !VRRegMO.getSubReg() && "Unexpected subreg!");
       if (!MRI->isReserved(PhysReg) && !is_contained(Hints, PhysReg))
@@ -754,8 +753,7 @@ bool RISCVRegisterInfo::getRegAllocationHints(
     if (!MO.isReg())
       return true;
     Register Reg = MO.getReg();
-    Register PhysReg =
-        Register::isPhysicalRegister(Reg) ? Reg : Register(VRM->getPhys(Reg));
+    Register PhysReg = Reg.isPhysical() ? Reg : Register(VRM->getPhys(Reg));
     return PhysReg && RISCV::GPRCRegClass.contains(PhysReg);
   };