[llvm] 8fd5558 - [NFC] Use TypeSize::geFixedValue() instead of TypeSize::getFixedSize()
Guillaume Chatelet via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 11 08:49:51 PST 2023
Author: Guillaume Chatelet
Date: 2023-01-11T16:49:38Z
New Revision: 8fd5558b29761aec91143129cb23c90581a944e9
URL: https://github.com/llvm/llvm-project/commit/8fd5558b29761aec91143129cb23c90581a944e9
DIFF: https://github.com/llvm/llvm-project/commit/8fd5558b29761aec91143129cb23c90581a944e9.diff
LOG: [NFC] Use TypeSize::geFixedValue() instead of TypeSize::getFixedSize()
This change is one of a series to implement the discussion from
https://reviews.llvm.org/D141134.
Added:
Modified:
llvm/include/llvm/Analysis/MemoryLocation.h
llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
llvm/include/llvm/CodeGen/ValueTypes.h
llvm/include/llvm/IR/DataLayout.h
llvm/include/llvm/Support/LowLevelTypeImpl.h
llvm/include/llvm/Support/MachineValueType.h
llvm/lib/Analysis/BasicAliasAnalysis.cpp
llvm/lib/Analysis/ConstantFolding.cpp
llvm/lib/Analysis/IVDescriptors.cpp
llvm/lib/Analysis/Loads.cpp
llvm/lib/Analysis/LoopAccessAnalysis.cpp
llvm/lib/Analysis/StackSafetyAnalysis.cpp
llvm/lib/Analysis/ValueTracking.cpp
llvm/lib/CodeGen/Analysis.cpp
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/CodeGenPrepare.cpp
llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
llvm/lib/CodeGen/GlobalMerge.cpp
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/TypePromotion.cpp
llvm/lib/IR/AutoUpgrade.cpp
llvm/lib/IR/DataLayout.cpp
llvm/lib/IR/Type.cpp
llvm/lib/IR/Value.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
llvm/lib/Target/Mips/MipsISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86InterleavedAccess.cpp
llvm/lib/Target/X86/X86TargetTransformInfo.cpp
llvm/lib/Transforms/Coroutines/CoroFrame.cpp
llvm/lib/Transforms/IPO/AttributorAttributes.cpp
llvm/lib/Transforms/IPO/GlobalOpt.cpp
llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
llvm/lib/Transforms/Scalar/LICM.cpp
llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
llvm/lib/Transforms/Scalar/LoopPredication.cpp
llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
llvm/lib/Transforms/Scalar/NaryReassociate.cpp
llvm/lib/Transforms/Scalar/SROA.cpp
llvm/lib/Transforms/Utils/FunctionComparator.cpp
llvm/lib/Transforms/Utils/InlineFunction.cpp
llvm/lib/Transforms/Utils/Local.cpp
llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
llvm/lib/Transforms/Utils/VNCoercion.cpp
llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
llvm/unittests/AsmParser/AsmParserTest.cpp
llvm/unittests/IR/VectorTypesTest.cpp
llvm/unittests/Support/TypeSizeTest.cpp
llvm/utils/TableGen/GlobalISelEmitter.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/Analysis/MemoryLocation.h b/llvm/include/llvm/Analysis/MemoryLocation.h
index 0dba415b78af4..85ca84e68a139 100644
--- a/llvm/include/llvm/Analysis/MemoryLocation.h
+++ b/llvm/include/llvm/Analysis/MemoryLocation.h
@@ -103,7 +103,7 @@ class LocationSize {
static LocationSize precise(TypeSize Value) {
if (Value.isScalable())
return afterPointer();
- return precise(Value.getFixedSize());
+ return precise(Value.getFixedValue());
}
static LocationSize upperBound(uint64_t Value) {
@@ -117,7 +117,7 @@ class LocationSize {
static LocationSize upperBound(TypeSize Value) {
if (Value.isScalable())
return afterPointer();
- return upperBound(Value.getFixedSize());
+ return upperBound(Value.getFixedValue());
}
/// Any location after the base pointer (but still within the underlying
@@ -283,7 +283,7 @@ class MemoryLocation {
// Return the exact size if the exact size is known at compiletime,
// otherwise return MemoryLocation::UnknownSize.
static uint64_t getSizeOrUnknown(const TypeSize &T) {
- return T.isScalable() ? UnknownSize : T.getFixedSize();
+ return T.isScalable() ? UnknownSize : T.getFixedValue();
}
MemoryLocation() : Ptr(nullptr), Size(LocationSize::beforeOrAfterPointer()) {}
diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
index 262b42a05d993..0cd68dffd5e4a 100644
--- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
+++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
@@ -555,7 +555,7 @@ class TargetTransformInfoImplBase {
// trunc to a native type is free (assuming the target has compare and
// shift-right of the same width).
TypeSize DstSize = DL.getTypeSizeInBits(Dst);
- if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedSize()))
+ if (!DstSize.isScalable() && DL.isLegalInteger(DstSize.getFixedValue()))
return 0;
break;
}
@@ -872,7 +872,7 @@ class TargetTransformInfoImplBase {
// The max required size is the size of the vector element type
unsigned MaxRequiredSize =
- VT->getElementType()->getPrimitiveSizeInBits().getFixedSize();
+ VT->getElementType()->getPrimitiveSizeInBits().getFixedValue();
unsigned MinRequiredSize = 0;
for (unsigned i = 0, e = VT->getNumElements(); i < e; ++i) {
@@ -992,7 +992,7 @@ class TargetTransformInfoImplCRTPBase : public TargetTransformInfoImplBase {
if (isa<ScalableVectorType>(TargetType))
return TTI::TCC_Basic;
int64_t ElementSize =
- DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize();
+ DL.getTypeAllocSize(GTI.getIndexedType()).getFixedValue();
if (ConstIdx) {
BaseOffset +=
ConstIdx->getValue().sextOrTrunc(PtrSizeBits) * ElementSize;
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.h b/llvm/include/llvm/CodeGen/ValueTypes.h
index 6917fa988b7db..ca55b7d430683 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.h
+++ b/llvm/include/llvm/CodeGen/ValueTypes.h
@@ -346,11 +346,11 @@ namespace llvm {
/// Return the size of the specified fixed width value type in bits. The
/// function will assert if the type is scalable.
uint64_t getFixedSizeInBits() const {
- return getSizeInBits().getFixedSize();
+ return getSizeInBits().getFixedValue();
}
uint64_t getScalarSizeInBits() const {
- return getScalarType().getSizeInBits().getFixedSize();
+ return getScalarType().getSizeInBits().getFixedValue();
}
/// Return the number of bytes overwritten by a store of the specified value
@@ -367,7 +367,7 @@ namespace llvm {
// Return the number of bytes overwritten by a store of this value type or
// this value type's element type in the case of a vector.
uint64_t getScalarStoreSize() const {
- return getScalarType().getStoreSize().getFixedSize();
+ return getScalarType().getStoreSize().getFixedValue();
}
/// Return the number of bits overwritten by a store of the specified value
diff --git a/llvm/include/llvm/IR/DataLayout.h b/llvm/include/llvm/IR/DataLayout.h
index 3ac9c74ab0678..b869d2c047031 100644
--- a/llvm/include/llvm/IR/DataLayout.h
+++ b/llvm/include/llvm/IR/DataLayout.h
@@ -710,7 +710,7 @@ inline TypeSize DataLayout::getTypeSizeInBits(Type *Ty) const {
VectorType *VTy = cast<VectorType>(Ty);
auto EltCnt = VTy->getElementCount();
uint64_t MinBits = EltCnt.getKnownMinValue() *
- getTypeSizeInBits(VTy->getElementType()).getFixedSize();
+ getTypeSizeInBits(VTy->getElementType()).getFixedValue();
return TypeSize(MinBits, EltCnt.isScalable());
}
case Type::TargetExtTyID: {
diff --git a/llvm/include/llvm/Support/LowLevelTypeImpl.h b/llvm/include/llvm/Support/LowLevelTypeImpl.h
index aeedec00dbb08..f33c1ecde0394 100644
--- a/llvm/include/llvm/Support/LowLevelTypeImpl.h
+++ b/llvm/include/llvm/Support/LowLevelTypeImpl.h
@@ -63,9 +63,11 @@ class LLT {
static constexpr LLT vector(ElementCount EC, LLT ScalarTy) {
assert(!EC.isScalar() && "invalid number of vector elements");
assert(!ScalarTy.isVector() && "invalid vector element type");
- return LLT{ScalarTy.isPointer(), /*isVector=*/true, /*isScalar=*/false,
+ return LLT{ScalarTy.isPointer(),
+ /*isVector=*/true,
+ /*isScalar=*/false,
EC,
- ScalarTy.getSizeInBits().getFixedSize(),
+ ScalarTy.getSizeInBits().getFixedValue(),
ScalarTy.isPointer() ? ScalarTy.getAddressSpace() : 0};
}
diff --git a/llvm/include/llvm/Support/MachineValueType.h b/llvm/include/llvm/Support/MachineValueType.h
index aa4a9a35b4ad4..d7ad32737a457 100644
--- a/llvm/include/llvm/Support/MachineValueType.h
+++ b/llvm/include/llvm/Support/MachineValueType.h
@@ -1132,11 +1132,11 @@ namespace llvm {
/// Return the size of the specified fixed width value type in bits. The
/// function will assert if the type is scalable.
uint64_t getFixedSizeInBits() const {
- return getSizeInBits().getFixedSize();
+ return getSizeInBits().getFixedValue();
}
uint64_t getScalarSizeInBits() const {
- return getScalarType().getSizeInBits().getFixedSize();
+ return getScalarType().getSizeInBits().getFixedValue();
}
/// Return the number of bytes overwritten by a store of the specified value
@@ -1153,7 +1153,7 @@ namespace llvm {
// Return the number of bytes overwritten by a store of this value type or
// this value type's element type in the case of a vector.
uint64_t getScalarStoreSize() const {
- return getScalarType().getStoreSize().getFixedSize();
+ return getScalarType().getStoreSize().getFixedValue();
}
/// Return the number of bits overwritten by a store of the specified value
diff --git a/llvm/lib/Analysis/BasicAliasAnalysis.cpp b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
index 1ea1d4196f80b..dc728c1cbfebc 100644
--- a/llvm/lib/Analysis/BasicAliasAnalysis.cpp
+++ b/llvm/lib/Analysis/BasicAliasAnalysis.cpp
@@ -614,7 +614,7 @@ BasicAAResult::DecomposeGEPExpression(const Value *V, const DataLayout &DL,
return Decomposed;
}
- Decomposed.Offset += AllocTypeSize.getFixedSize() *
+ Decomposed.Offset += AllocTypeSize.getFixedValue() *
CIdx->getValue().sextOrTrunc(MaxIndexSize);
continue;
}
@@ -636,7 +636,7 @@ BasicAAResult::DecomposeGEPExpression(const Value *V, const DataLayout &DL,
CastedValue(Index, 0, SExtBits, TruncBits), DL, 0, AC, DT);
// Scale by the type size.
- unsigned TypeSize = AllocTypeSize.getFixedSize();
+ unsigned TypeSize = AllocTypeSize.getFixedValue();
LE = LE.mul(APInt(IndexSize, TypeSize), GEPOp->isInBounds());
Decomposed.Offset += LE.Offset.sext(MaxIndexSize);
APInt Scale = LE.Scale.sext(MaxIndexSize);
diff --git a/llvm/lib/Analysis/ConstantFolding.cpp b/llvm/lib/Analysis/ConstantFolding.cpp
index 7a601ad904168..3f8cd86cb2c2e 100644
--- a/llvm/lib/Analysis/ConstantFolding.cpp
+++ b/llvm/lib/Analysis/ConstantFolding.cpp
@@ -561,8 +561,8 @@ Constant *FoldReinterpretLoadFromConst(Constant *C, Type *LoadTy,
!LoadTy->isVectorTy())
return nullptr;
- Type *MapTy = Type::getIntNTy(
- C->getContext(), DL.getTypeSizeInBits(LoadTy).getFixedSize());
+ Type *MapTy = Type::getIntNTy(C->getContext(),
+ DL.getTypeSizeInBits(LoadTy).getFixedValue());
if (Constant *Res = FoldReinterpretLoadFromConst(C, MapTy, Offset, DL)) {
if (Res->isNullValue() && !LoadTy->isX86_MMXTy() &&
!LoadTy->isX86_AMXTy())
@@ -705,7 +705,7 @@ Constant *llvm::ConstantFoldLoadFromConst(Constant *C, Type *Ty,
// Explicitly check for out-of-bounds access, so we return poison even if the
// constant is a uniform value.
TypeSize Size = DL.getTypeAllocSize(C->getType());
- if (!Size.isScalable() && Offset.sge(Size.getFixedSize()))
+ if (!Size.isScalable() && Offset.sge(Size.getFixedValue()))
return PoisonValue::get(Ty);
// Try an offset-independent fold of a uniform value.
diff --git a/llvm/lib/Analysis/IVDescriptors.cpp b/llvm/lib/Analysis/IVDescriptors.cpp
index c76155832bce3..d37d0d4845431 100644
--- a/llvm/lib/Analysis/IVDescriptors.cpp
+++ b/llvm/lib/Analysis/IVDescriptors.cpp
@@ -1585,7 +1585,7 @@ bool InductionDescriptor::isInductionPHI(
if (TySize.isZero() || TySize.isScalable())
return false;
- int64_t Size = static_cast<int64_t>(TySize.getFixedSize());
+ int64_t Size = static_cast<int64_t>(TySize.getFixedValue());
int64_t CVSize = CV->getSExtValue();
if (CVSize % Size)
return false;
diff --git a/llvm/lib/Analysis/Loads.cpp b/llvm/lib/Analysis/Loads.cpp
index e108df8473210..f55333303f8d9 100644
--- a/llvm/lib/Analysis/Loads.cpp
+++ b/llvm/lib/Analysis/Loads.cpp
@@ -267,7 +267,7 @@ bool llvm::isDereferenceableAndAlignedInLoop(LoadInst *LI, Loop *L,
Value *Ptr = LI->getPointerOperand();
APInt EltSize(DL.getIndexTypeSizeInBits(Ptr->getType()),
- DL.getTypeStoreSize(LI->getType()).getFixedSize());
+ DL.getTypeStoreSize(LI->getType()).getFixedValue());
const Align Alignment = LI->getAlign();
Instruction *HeaderFirstNonPHI = L->getHeader()->getFirstNonPHI();
@@ -539,7 +539,7 @@ static Value *getAvailableLoadStore(Instruction *Inst, const Value *Ptr,
return nullptr;
// Make sure the read bytes are contained in the memset.
- uint64_t LoadSize = LoadTypeSize.getFixedSize();
+ uint64_t LoadSize = LoadTypeSize.getFixedValue();
if ((Len->getValue() * 8).ult(LoadSize))
return nullptr;
diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
index 6cddf424bf331..9e110567e98e4 100644
--- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp
+++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp
@@ -1441,7 +1441,7 @@ std::optional<int64_t> llvm::getPtrStride(PredicatedScalarEvolution &PSE,
auto &DL = Lp->getHeader()->getModule()->getDataLayout();
TypeSize AllocSize = DL.getTypeAllocSize(AccessTy);
- int64_t Size = AllocSize.getFixedSize();
+ int64_t Size = AllocSize.getFixedValue();
const APInt &APStepVal = C->getAPInt();
// Huge step value - give up.
diff --git a/llvm/lib/Analysis/StackSafetyAnalysis.cpp b/llvm/lib/Analysis/StackSafetyAnalysis.cpp
index 9698af3ca85c3..606397727b01f 100644
--- a/llvm/lib/Analysis/StackSafetyAnalysis.cpp
+++ b/llvm/lib/Analysis/StackSafetyAnalysis.cpp
@@ -159,7 +159,7 @@ ConstantRange getStaticAllocaSizeRange(const AllocaInst &AI) {
ConstantRange R = ConstantRange::getEmpty(PointerSize);
if (TS.isScalable())
return R;
- APInt APSize(PointerSize, TS.getFixedSize(), true);
+ APInt APSize(PointerSize, TS.getFixedValue(), true);
if (APSize.isNonPositive())
return R;
if (AI.isArrayAllocation()) {
@@ -307,7 +307,7 @@ ConstantRange StackSafetyLocalAnalysis::getAccessRange(Value *Addr, Value *Base,
TypeSize Size) {
if (Size.isScalable())
return UnknownRange;
- APInt APSize(PointerSize, Size.getFixedSize(), true);
+ APInt APSize(PointerSize, Size.getFixedValue(), true);
if (APSize.isNegative())
return UnknownRange;
return getAccessRange(Addr, Base,
@@ -348,7 +348,7 @@ bool StackSafetyLocalAnalysis::isSafeAccess(const Use &U, AllocaInst *AI,
if (TS.isScalable())
return false;
auto *CalculationTy = IntegerType::getIntNTy(SE.getContext(), PointerSize);
- const SCEV *SV = SE.getConstant(CalculationTy, TS.getFixedSize());
+ const SCEV *SV = SE.getConstant(CalculationTy, TS.getFixedValue());
return isSafeAccess(U, AI, SV);
}
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index ac8ec77bee5bd..f2a63e7294db3 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -2573,16 +2573,16 @@ bool isKnownNonZero(const Value *V, const APInt &DemandedElts, unsigned Depth,
// truncating casts, e.g., int2ptr/ptr2int with appropriate sizes, as well
// as casts that can alter the value, e.g., AddrSpaceCasts.
if (!isa<ScalableVectorType>(I->getType()) &&
- Q.DL.getTypeSizeInBits(I->getOperand(0)->getType()).getFixedSize() <=
- Q.DL.getTypeSizeInBits(I->getType()).getFixedSize())
+ Q.DL.getTypeSizeInBits(I->getOperand(0)->getType()).getFixedValue() <=
+ Q.DL.getTypeSizeInBits(I->getType()).getFixedValue())
return isKnownNonZero(I->getOperand(0), Depth, Q);
break;
case Instruction::PtrToInt:
// Similar to int2ptr above, we can look through ptr2int here if the cast
// is a no-op or an extend and not a truncate.
if (!isa<ScalableVectorType>(I->getType()) &&
- Q.DL.getTypeSizeInBits(I->getOperand(0)->getType()).getFixedSize() <=
- Q.DL.getTypeSizeInBits(I->getType()).getFixedSize())
+ Q.DL.getTypeSizeInBits(I->getOperand(0)->getType()).getFixedValue() <=
+ Q.DL.getTypeSizeInBits(I->getType()).getFixedValue())
return isKnownNonZero(I->getOperand(0), Depth, Q);
break;
case Instruction::Or:
@@ -4331,7 +4331,7 @@ bool llvm::getConstantDataArrayInfo(const Value *V,
if (GV->getInitializer()->isNullValue()) {
Type *GVTy = GV->getValueType();
- uint64_t SizeInBytes = DL.getTypeStoreSize(GVTy).getFixedSize();
+ uint64_t SizeInBytes = DL.getTypeStoreSize(GVTy).getFixedValue();
uint64_t Length = SizeInBytes / ElementSizeInBytes;
Slice.Array = nullptr;
@@ -7487,7 +7487,7 @@ getOffsetFromIndex(const GEPOperator *GEP, unsigned Idx, const DataLayout &DL) {
TypeSize Size = DL.getTypeAllocSize(GTI.getIndexedType());
if (Size.isScalable())
return std::nullopt;
- Offset += Size.getFixedSize() * OpC->getSExtValue();
+ Offset += Size.getFixedValue() * OpC->getSExtValue();
}
return Offset;
diff --git a/llvm/lib/CodeGen/Analysis.cpp b/llvm/lib/CodeGen/Analysis.cpp
index f5dbaccfcad50..b9579441a0ba0 100644
--- a/llvm/lib/CodeGen/Analysis.cpp
+++ b/llvm/lib/CodeGen/Analysis.cpp
@@ -319,8 +319,9 @@ static const Value *getNoopInput(const Value *V,
NoopInput = Op;
} else if (isa<TruncInst>(I) &&
TLI.allowTruncateForTailCall(Op->getType(), I->getType())) {
- DataBits = std::min((uint64_t)DataBits,
- I->getType()->getPrimitiveSizeInBits().getFixedSize());
+ DataBits =
+ std::min((uint64_t)DataBits,
+ I->getType()->getPrimitiveSizeInBits().getFixedValue());
NoopInput = Op;
} else if (auto *CB = dyn_cast<CallBase>(I)) {
const Value *ReturnedOp = CB->getReturnedArgOperand();
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 5375c14648210..0f5e1648f09d7 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -2930,8 +2930,8 @@ const MCExpr *AsmPrinter::lowerConstant(const Constant *CV) {
//
// If the pointer is larger than the resultant integer, then
// as with Trunc just depend on the assembler to truncate it.
- if (DL.getTypeAllocSize(Ty).getFixedSize() <=
- DL.getTypeAllocSize(Op->getType()).getFixedSize())
+ if (DL.getTypeAllocSize(Ty).getFixedValue() <=
+ DL.getTypeAllocSize(Op->getType()).getFixedValue())
return OpExpr;
break; // Error
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index 31caa65425c51..87ba74b0106b3 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -4694,7 +4694,7 @@ bool AddressingModeMatcher::matchOperationAddr(User *AddrInst, unsigned Opcode,
// The optimisations below currently only work for fixed offsets.
if (TS.isScalable())
return false;
- int64_t TypeSize = TS.getFixedSize();
+ int64_t TypeSize = TS.getFixedValue();
if (ConstantInt *CI =
dyn_cast<ConstantInt>(AddrInst->getOperand(i))) {
const APInt &CVal = CI->getValue();
diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
index f145ce30e88d2..15d6cbcf6a7dd 100644
--- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
@@ -386,7 +386,7 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef<Register> OrigRegs,
assert(OrigRegs.size() == 1);
LLT OrigTy = MRI.getType(OrigRegs[0]);
- unsigned SrcSize = PartLLT.getSizeInBits().getFixedSize() * Regs.size();
+ unsigned SrcSize = PartLLT.getSizeInBits().getFixedValue() * Regs.size();
if (SrcSize == OrigTy.getSizeInBits())
B.buildMerge(OrigRegs[0], Regs);
else {
diff --git a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
index f5fa5fe6fe6e2..7c6eac8c8ce0e 100644
--- a/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LoadStoreOpt.cpp
@@ -306,7 +306,7 @@ bool LoadStoreOpt::mergeStores(SmallVectorImpl<GStore *> &StoresToMerge) {
bool AnyMerged = false;
do {
unsigned NumPow2 = PowerOf2Floor(StoresToMerge.size());
- unsigned MaxSizeBits = NumPow2 * OrigTy.getSizeInBits().getFixedSize();
+ unsigned MaxSizeBits = NumPow2 * OrigTy.getSizeInBits().getFixedValue();
// Compute the biggest store we can generate to handle the number of stores.
unsigned MergeSizeBits;
for (MergeSizeBits = MaxSizeBits; MergeSizeBits > 1; MergeSizeBits /= 2) {
@@ -352,7 +352,7 @@ bool LoadStoreOpt::doSingleStoreMerge(SmallVectorImpl<GStore *> &Stores) {
const unsigned NumStores = Stores.size();
LLT SmallTy = MRI->getType(FirstStore->getValueReg());
LLT WideValueTy =
- LLT::scalar(NumStores * SmallTy.getSizeInBits().getFixedSize());
+ LLT::scalar(NumStores * SmallTy.getSizeInBits().getFixedValue());
// For each store, compute pairwise merged debug locs.
DebugLoc MergedLoc = Stores.front()->getDebugLoc();
diff --git a/llvm/lib/CodeGen/GlobalMerge.cpp b/llvm/lib/CodeGen/GlobalMerge.cpp
index 075f14c871427..2ccf2def48f8e 100644
--- a/llvm/lib/CodeGen/GlobalMerge.cpp
+++ b/llvm/lib/CodeGen/GlobalMerge.cpp
@@ -225,8 +225,8 @@ bool GlobalMerge::doMerge(SmallVectorImpl<GlobalVariable*> &Globals,
llvm::stable_sort(
Globals, [&DL](const GlobalVariable *GV1, const GlobalVariable *GV2) {
// We don't support scalable global variables.
- return DL.getTypeAllocSize(GV1->getValueType()).getFixedSize() <
- DL.getTypeAllocSize(GV2->getValueType()).getFixedSize();
+ return DL.getTypeAllocSize(GV1->getValueType()).getFixedValue() <
+ DL.getTypeAllocSize(GV2->getValueType()).getFixedValue();
});
// If we want to just blindly group all globals together, do so.
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ca3cd95dbb701..278d82c26b5f6 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13292,8 +13292,8 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
auto AdjustBigEndianShift = [&](unsigned ShAmt) {
unsigned LVTStoreBits =
- LN0->getMemoryVT().getStoreSizeInBits().getFixedSize();
- unsigned EVTStoreBits = ExtVT.getStoreSizeInBits().getFixedSize();
+ LN0->getMemoryVT().getStoreSizeInBits().getFixedValue();
+ unsigned EVTStoreBits = ExtVT.getStoreSizeInBits().getFixedValue();
return LVTStoreBits - EVTStoreBits - ShAmt;
};
@@ -17208,8 +17208,8 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
// n:th least significant byte of the stored value.
int64_t OrigOffset = Offset;
if (DAG.getDataLayout().isBigEndian())
- Offset = ((int64_t)STMemType.getStoreSizeInBits().getFixedSize() -
- (int64_t)LDMemType.getStoreSizeInBits().getFixedSize()) /
+ Offset = ((int64_t)STMemType.getStoreSizeInBits().getFixedValue() -
+ (int64_t)LDMemType.getStoreSizeInBits().getFixedValue()) /
8 -
Offset;
@@ -17221,8 +17221,8 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
if (LdStScalable)
STCoversLD = (Offset == 0) && LdMemSize == StMemSize;
else
- STCoversLD = (Offset >= 0) && (Offset * 8 + LdMemSize.getFixedSize() <=
- StMemSize.getFixedSize());
+ STCoversLD = (Offset >= 0) && (Offset * 8 + LdMemSize.getFixedValue() <=
+ StMemSize.getFixedValue());
auto ReplaceLd = [&](LoadSDNode *LD, SDValue Val, SDValue Chain) -> SDValue {
if (LD->isIndexed()) {
@@ -17251,7 +17251,7 @@ SDValue DAGCombiner::ForwardStoreValueToDirectLoad(LoadSDNode *LD) {
// Mask to size of LDMemType
auto Mask =
DAG.getConstant(APInt::getLowBitsSet(STType.getFixedSizeInBits(),
- StMemSize.getFixedSize()),
+ StMemSize.getFixedValue()),
SDLoc(ST), STType);
auto Val = DAG.getNode(ISD::AND, SDLoc(LD), LDType, ST->getValue(), Mask);
return ReplaceLd(LD, Val, Chain);
@@ -18277,7 +18277,7 @@ SDValue DAGCombiner::TransformFPLoadStorePair(SDNode *N) {
return SDValue();
unsigned FastLD = 0, FastST = 0;
- EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedSize());
+ EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VTSize.getFixedValue());
if (!TLI.isOperationLegal(ISD::LOAD, IntVT) ||
!TLI.isOperationLegal(ISD::STORE, IntVT) ||
!TLI.isDesirableToTransformToIntegerOp(ISD::LOAD, VT) ||
@@ -19781,7 +19781,7 @@ SDValue DAGCombiner::visitLIFETIME_END(SDNode *N) {
// If we store purely within object bounds just before its lifetime ends,
// we can remove the store.
if (LifetimeEndBase.contains(DAG, LifetimeEnd->getSize() * 8, StoreBase,
- StoreSize.getFixedSize() * 8)) {
+ StoreSize.getFixedValue() * 8)) {
LLVM_DEBUG(dbgs() << "\nRemoving store:"; StoreBase.dump();
dbgs() << "\nwithin LIFETIME_END of : ";
LifetimeEndBase.dump(); dbgs() << "\n");
@@ -21563,7 +21563,7 @@ SDValue DAGCombiner::convertBuildVecZextToBuildVecWithZeros(SDNode *N) {
if (Op.getOpcode() != ISD::ZERO_EXTEND)
return SDValue();
unsigned CurrActiveBits =
- Op.getOperand(0).getValueSizeInBits().getFixedSize();
+ Op.getOperand(0).getValueSizeInBits().getFixedValue();
assert(!ActiveBits && "Already encountered non-constant-zero operand?");
ActiveBits = CurrActiveBits;
// We want to at least halve the element size.
@@ -22476,7 +22476,7 @@ static SDValue narrowExtractedVectorLoad(SDNode *Extract, SelectionDAG &DAG) {
MachinePointerInfo(Ld->getPointerInfo().getAddrSpace());
MMO = MF.getMachineMemOperand(Ld->getMemOperand(), MPI, StoreSize);
} else
- MMO = MF.getMachineMemOperand(Ld->getMemOperand(), Offset.getFixedSize(),
+ MMO = MF.getMachineMemOperand(Ld->getMemOperand(), Offset.getFixedValue(),
StoreSize);
SDValue NewLd = DAG.getLoad(VT, DL, Ld->getChain(), NewAddr, MMO);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index edc6a43a504b1..c3106216a0609 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -552,16 +552,16 @@ void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) {
// Promote to a byte-sized store with upper bits zero if not
// storing an integral number of bytes. For example, promote
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
- EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StSize.getFixedSize());
+ EVT NVT = EVT::getIntegerVT(*DAG.getContext(), StSize.getFixedValue());
Value = DAG.getZeroExtendInReg(Value, dl, StVT);
SDValue Result =
DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), NVT,
ST->getOriginalAlign(), MMOFlags, AAInfo);
ReplaceNode(SDValue(Node, 0), Result);
- } else if (!StVT.isVector() && !isPowerOf2_64(StWidth.getFixedSize())) {
+ } else if (!StVT.isVector() && !isPowerOf2_64(StWidth.getFixedValue())) {
// If not storing a power-of-2 number of bits, expand as two stores.
assert(!StVT.isVector() && "Unsupported truncstore!");
- unsigned StWidthBits = StWidth.getFixedSize();
+ unsigned StWidthBits = StWidth.getFixedValue();
unsigned LogStWidth = Log2_32(StWidthBits);
assert(LogStWidth < 32);
unsigned RoundWidth = 1 << LogStWidth;
@@ -772,7 +772,7 @@ void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) {
} else if (!isPowerOf2_64(SrcWidth.getKnownMinValue())) {
// If not loading a power-of-2 number of bits, expand as two loads.
assert(!SrcVT.isVector() && "Unsupported extload!");
- unsigned SrcWidthBits = SrcWidth.getFixedSize();
+ unsigned SrcWidthBits = SrcWidth.getFixedValue();
unsigned LogSrcWidth = Log2_32(SrcWidthBits);
assert(LogSrcWidth < 32);
unsigned RoundWidth = 1 << LogSrcWidth;
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
index 6fdd3fb7e0dc2..5e03495931393 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -763,7 +763,7 @@ void DAGTypeLegalizer::SetScalarizedVector(SDValue Op, SDValue Result) {
// a constant i8 operand.
// We don't currently support the scalarization of scalable vector types.
- assert(Result.getValueSizeInBits().getFixedSize() >=
+ assert(Result.getValueSizeInBits().getFixedValue() >=
Op.getScalarValueSizeInBits() &&
"Invalid type for scalarized vector");
AnalyzeNewValue(Result);
diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index f76c14f1a40a0..f7384ced3e23e 100644
--- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -1172,7 +1172,7 @@ void DAGTypeLegalizer::IncrementPointer(MemSDNode *N, EVT MemVT,
SDNodeFlags Flags;
SDValue BytesIncrement = DAG.getVScale(
DL, Ptr.getValueType(),
- APInt(Ptr.getValueSizeInBits().getFixedSize(), IncrementSize));
+ APInt(Ptr.getValueSizeInBits().getFixedValue(), IncrementSize));
MPI = MachinePointerInfo(N->getPointerInfo().getAddrSpace());
Flags.setNoUnsignedWrap(true);
if (ScaledOffset)
@@ -1927,7 +1927,7 @@ void DAGTypeLegalizer::SplitVecRes_VP_LOAD(VPLoadSDNode *LD, SDValue &Lo,
MPI = MachinePointerInfo(LD->getPointerInfo().getAddrSpace());
else
MPI = LD->getPointerInfo().getWithOffset(
- LoMemVT.getStoreSize().getFixedSize());
+ LoMemVT.getStoreSize().getFixedValue());
MMO = DAG.getMachineFunction().getMachineMemOperand(
MPI, MachineMemOperand::MOLoad, MemoryLocation::UnknownSize, Alignment,
@@ -2091,7 +2091,7 @@ void DAGTypeLegalizer::SplitVecRes_MLOAD(MaskedLoadSDNode *MLD,
MPI = MachinePointerInfo(MLD->getPointerInfo().getAddrSpace());
else
MPI = MLD->getPointerInfo().getWithOffset(
- LoMemVT.getStoreSize().getFixedSize());
+ LoMemVT.getStoreSize().getFixedValue());
MMO = DAG.getMachineFunction().getMachineMemOperand(
MPI, MachineMemOperand::MOLoad, MemoryLocation::UnknownSize, Alignment,
@@ -3314,7 +3314,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_VP_STORE(VPStoreSDNode *N, unsigned OpNo) {
MPI = MachinePointerInfo(N->getPointerInfo().getAddrSpace());
} else
MPI = N->getPointerInfo().getWithOffset(
- LoMemVT.getStoreSize().getFixedSize());
+ LoMemVT.getStoreSize().getFixedValue());
MMO = DAG.getMachineFunction().getMachineMemOperand(
MPI, MachineMemOperand::MOStore, MemoryLocation::UnknownSize, Alignment,
@@ -3464,7 +3464,7 @@ SDValue DAGTypeLegalizer::SplitVecOp_MSTORE(MaskedStoreSDNode *N,
MPI = MachinePointerInfo(N->getPointerInfo().getAddrSpace());
} else
MPI = N->getPointerInfo().getWithOffset(
- LoMemVT.getStoreSize().getFixedSize());
+ LoMemVT.getStoreSize().getFixedValue());
MMO = DAG.getMachineFunction().getMachineMemOperand(
MPI, MachineMemOperand::MOStore, MemoryLocation::UnknownSize, Alignment,
@@ -6770,7 +6770,7 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
assert(TypeSize::isKnownLE(LdWidth, FirstVTWidth));
if (!FirstVT->isVector()) {
unsigned NumElts =
- WidenWidth.getFixedSize() / FirstVTWidth.getFixedSize();
+ WidenWidth.getFixedValue() / FirstVTWidth.getFixedValue();
EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), *FirstVT, NumElts);
SDValue VecOp = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, NewVecVT, LdOp);
return DAG.getNode(ISD::BITCAST, dl, WidenVT, VecOp);
@@ -6779,9 +6779,9 @@ SDValue DAGTypeLegalizer::GenWidenVectorLoads(SmallVectorImpl<SDValue> &LdChain,
return LdOp;
// TODO: We don't currently have any tests that exercise this code path.
- assert(WidenWidth.getFixedSize() % FirstVTWidth.getFixedSize() == 0);
+ assert(WidenWidth.getFixedValue() % FirstVTWidth.getFixedValue() == 0);
unsigned NumConcat =
- WidenWidth.getFixedSize() / FirstVTWidth.getFixedSize();
+ WidenWidth.getFixedValue() / FirstVTWidth.getFixedValue();
SmallVector<SDValue, 16> ConcatOps(NumConcat);
SDValue UndefVal = DAG.getUNDEF(*FirstVT);
ConcatOps[0] = LdOp;
@@ -7003,11 +7003,11 @@ bool DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
} while (--Count);
} else {
// Cast the vector to the scalar type we can store.
- unsigned NumElts = ValWidth.getFixedSize() / NewVTWidth.getFixedSize();
+ unsigned NumElts = ValWidth.getFixedValue() / NewVTWidth.getFixedValue();
EVT NewVecVT = EVT::getVectorVT(*DAG.getContext(), NewVT, NumElts);
SDValue VecOp = DAG.getNode(ISD::BITCAST, dl, NewVecVT, ValOp);
// Readjust index position based on new vector type.
- Idx = Idx * ValEltWidth / NewVTWidth.getFixedSize();
+ Idx = Idx * ValEltWidth / NewVTWidth.getFixedValue();
do {
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, VecOp,
DAG.getVectorIdxConstant(Idx++, dl));
@@ -7019,7 +7019,7 @@ bool DAGTypeLegalizer::GenWidenVectorStores(SmallVectorImpl<SDValue> &StChain,
IncrementPointer(cast<StoreSDNode>(PartStore), NewVT, MPI, BasePtr);
} while (--Count);
// Restore index back to be relative to the original widen element type.
- Idx = Idx * NewVTWidth.getFixedSize() / ValEltWidth;
+ Idx = Idx * NewVTWidth.getFixedValue() / ValEltWidth;
}
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 12c76ba7b685a..936aab230efb1 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -6894,10 +6894,10 @@ SDValue SelectionDAG::getMemBasePlusOffset(SDValue Base, TypeSize Offset,
if (Offset.isScalable())
Index = getVScale(DL, Base.getValueType(),
- APInt(Base.getValueSizeInBits().getFixedSize(),
+ APInt(Base.getValueSizeInBits().getFixedValue(),
Offset.getKnownMinValue()));
else
- Index = getConstant(Offset.getFixedSize(), DL, VT);
+ Index = getConstant(Offset.getFixedValue(), DL, VT);
return getMemBasePlusOffset(Base, Index, DL, Flags);
}
diff --git a/llvm/lib/CodeGen/TypePromotion.cpp b/llvm/lib/CodeGen/TypePromotion.cpp
index 82ad80634277e..e6c0b3242d678 100644
--- a/llvm/lib/CodeGen/TypePromotion.cpp
+++ b/llvm/lib/CodeGen/TypePromotion.cpp
@@ -774,7 +774,7 @@ bool TypePromotionImpl::isLegalToPromote(Value *V) {
bool TypePromotionImpl::TryToPromote(Value *V, unsigned PromotedWidth,
const LoopInfo &LI) {
Type *OrigTy = V->getType();
- TypeSize = OrigTy->getPrimitiveSizeInBits().getFixedSize();
+ TypeSize = OrigTy->getPrimitiveSizeInBits().getFixedValue();
SafeToPromote.clear();
SafeWrap.clear();
@@ -919,7 +919,7 @@ bool TypePromotionImpl::run(Function &F, const TargetMachine *TM,
const TargetSubtargetInfo *SubtargetInfo = TM->getSubtargetImpl(F);
const TargetLowering *TLI = SubtargetInfo->getTargetLowering();
RegisterBitWidth =
- TTI.getRegisterBitWidth(TargetTransformInfo::RGK_Scalar).getFixedSize();
+ TTI.getRegisterBitWidth(TargetTransformInfo::RGK_Scalar).getFixedValue();
Ctx = &F.getParent()->getContext();
// Return the preferred integer width of the instruction, or zero if we
diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp
index c28b896d453f4..7b9c55ff30a50 100644
--- a/llvm/lib/IR/AutoUpgrade.cpp
+++ b/llvm/lib/IR/AutoUpgrade.cpp
@@ -1559,7 +1559,7 @@ static Value *UpgradeMaskedStore(IRBuilder<> &Builder,
llvm::PointerType::getUnqual(Data->getType()));
const Align Alignment =
Aligned
- ? Align(Data->getType()->getPrimitiveSizeInBits().getFixedSize() / 8)
+ ? Align(Data->getType()->getPrimitiveSizeInBits().getFixedValue() / 8)
: Align(1);
// If the mask is all ones just emit a regular store.
@@ -1581,8 +1581,9 @@ static Value *UpgradeMaskedLoad(IRBuilder<> &Builder,
Ptr = Builder.CreateBitCast(Ptr, llvm::PointerType::getUnqual(ValTy));
const Align Alignment =
Aligned
- ? Align(Passthru->getType()->getPrimitiveSizeInBits().getFixedSize() /
- 8)
+ ? Align(
+ Passthru->getType()->getPrimitiveSizeInBits().getFixedValue() /
+ 8)
: Align(1);
// If the mask is all ones just emit a regular store.
@@ -2135,7 +2136,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) {
"cast");
StoreInst *SI = Builder.CreateAlignedStore(
Arg1, BC,
- Align(Arg1->getType()->getPrimitiveSizeInBits().getFixedSize() / 8));
+ Align(Arg1->getType()->getPrimitiveSizeInBits().getFixedValue() / 8));
SI->setMetadata(M->getMDKindID("nontemporal"), Node);
// Remove intrinsic.
@@ -3475,7 +3476,7 @@ void llvm::UpgradeIntrinsicCall(CallBase *CI, Function *NewFn) {
Ptr, PointerType::getUnqual(CI->getType()), "cast");
LoadInst *LI = Builder.CreateAlignedLoad(
CI->getType(), BC,
- Align(CI->getType()->getPrimitiveSizeInBits().getFixedSize() / 8));
+ Align(CI->getType()->getPrimitiveSizeInBits().getFixedValue() / 8));
LI->setMetadata(M->getMDKindID("nontemporal"), Node);
Rep = LI;
} else if (IsX86 && (Name.startswith("fma.vfmadd.") ||
diff --git a/llvm/lib/IR/DataLayout.cpp b/llvm/lib/IR/DataLayout.cpp
index 20359f6524bae..7271d45d565a0 100644
--- a/llvm/lib/IR/DataLayout.cpp
+++ b/llvm/lib/IR/DataLayout.cpp
@@ -783,7 +783,7 @@ Align DataLayout::getAlignment(Type *Ty, bool abi_or_pref) const {
case Type::PPC_FP128TyID:
case Type::FP128TyID:
case Type::X86_FP80TyID: {
- unsigned BitWidth = getTypeSizeInBits(Ty).getFixedSize();
+ unsigned BitWidth = getTypeSizeInBits(Ty).getFixedValue();
auto I = findAlignmentLowerBound(FLOAT_ALIGN, BitWidth);
if (I != Alignments.end() && I->AlignType == FLOAT_ALIGN &&
I->TypeBitWidth == BitWidth)
@@ -938,7 +938,7 @@ std::optional<APInt> DataLayout::getGEPIndexForOffset(Type *&ElemTy,
if (auto *VecTy = dyn_cast<VectorType>(ElemTy)) {
ElemTy = VecTy->getElementType();
- unsigned ElemSizeInBits = getTypeSizeInBits(ElemTy).getFixedSize();
+ unsigned ElemSizeInBits = getTypeSizeInBits(ElemTy).getFixedValue();
// GEPs over non-multiple of 8 size vector elements are invalid.
if (ElemSizeInBits % 8 != 0)
return std::nullopt;
diff --git a/llvm/lib/IR/Type.cpp b/llvm/lib/IR/Type.cpp
index 8d28522c22c40..8bb8c9d29a624 100644
--- a/llvm/lib/IR/Type.cpp
+++ b/llvm/lib/IR/Type.cpp
@@ -117,18 +117,18 @@ bool Type::canLosslesslyBitCastTo(Type *Ty) const {
// 64-bit fixed width vector types can be losslessly converted to x86mmx.
if (((isa<FixedVectorType>(this)) && Ty->isX86_MMXTy()) &&
- getPrimitiveSizeInBits().getFixedSize() == 64)
+ getPrimitiveSizeInBits().getFixedValue() == 64)
return true;
if ((isX86_MMXTy() && isa<FixedVectorType>(Ty)) &&
- Ty->getPrimitiveSizeInBits().getFixedSize() == 64)
+ Ty->getPrimitiveSizeInBits().getFixedValue() == 64)
return true;
// 8192-bit fixed width vector types can be losslessly converted to x86amx.
if (((isa<FixedVectorType>(this)) && Ty->isX86_AMXTy()) &&
- getPrimitiveSizeInBits().getFixedSize() == 8192)
+ getPrimitiveSizeInBits().getFixedValue() == 8192)
return true;
if ((isX86_AMXTy() && isa<FixedVectorType>(Ty)) &&
- Ty->getPrimitiveSizeInBits().getFixedSize() == 8192)
+ Ty->getPrimitiveSizeInBits().getFixedValue() == 8192)
return true;
// At this point we have only various mismatches of the first class types
@@ -179,7 +179,7 @@ TypeSize Type::getPrimitiveSizeInBits() const {
ElementCount EC = VTy->getElementCount();
TypeSize ETS = VTy->getElementType()->getPrimitiveSizeInBits();
assert(!ETS.isScalable() && "Vector type should have fixed-width elements");
- return {ETS.getFixedSize() * EC.getKnownMinValue(), EC.isScalable()};
+ return {ETS.getFixedValue() * EC.getKnownMinValue(), EC.isScalable()};
}
default: return TypeSize::Fixed(0);
}
@@ -187,7 +187,7 @@ TypeSize Type::getPrimitiveSizeInBits() const {
unsigned Type::getScalarSizeInBits() const {
// It is safe to assume that the scalar types have a fixed size.
- return getScalarType()->getPrimitiveSizeInBits().getFixedSize();
+ return getScalarType()->getPrimitiveSizeInBits().getFixedValue();
}
int Type::getFPMantissaWidth() const {
diff --git a/llvm/lib/IR/Value.cpp b/llvm/lib/IR/Value.cpp
index 568b145e17aa6..fa22065dcf364 100644
--- a/llvm/lib/IR/Value.cpp
+++ b/llvm/lib/IR/Value.cpp
@@ -907,7 +907,7 @@ uint64_t Value::getPointerDereferenceableBytes(const DataLayout &DL,
if (GV->getValueType()->isSized() && !GV->hasExternalWeakLinkage()) {
// TODO: Don't outright reject hasExternalWeakLinkage but set the
// CanBeNull flag.
- DerefBytes = DL.getTypeStoreSize(GV->getValueType()).getFixedSize();
+ DerefBytes = DL.getTypeStoreSize(GV->getValueType()).getFixedValue();
CanBeNull = false;
CanBeFreed = false;
}
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 594397fc41168..24c72f95e0103 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -6595,10 +6595,10 @@ SDValue AArch64TargetLowering::LowerFormalArguments(
if (PartLoad.isScalableVector()) {
BytesIncrement = DAG.getVScale(
DL, Ptr.getValueType(),
- APInt(Ptr.getValueSizeInBits().getFixedSize(), PartSize));
+ APInt(Ptr.getValueSizeInBits().getFixedValue(), PartSize));
} else {
BytesIncrement = DAG.getConstant(
- APInt(Ptr.getValueSizeInBits().getFixedSize(), PartSize), DL,
+ APInt(Ptr.getValueSizeInBits().getFixedValue(), PartSize), DL,
Ptr.getValueType());
}
SDNodeFlags Flags;
@@ -7461,10 +7461,10 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
if (isScalable) {
BytesIncrement = DAG.getVScale(
DL, Ptr.getValueType(),
- APInt(Ptr.getValueSizeInBits().getFixedSize(), PartSize));
+ APInt(Ptr.getValueSizeInBits().getFixedValue(), PartSize));
} else {
BytesIncrement = DAG.getConstant(
- APInt(Ptr.getValueSizeInBits().getFixedSize(), PartSize), DL,
+ APInt(Ptr.getValueSizeInBits().getFixedValue(), PartSize), DL,
Ptr.getValueType());
}
SDNodeFlags Flags;
@@ -13675,8 +13675,8 @@ bool AArch64TargetLowering::shouldReduceLoadWidth(SDNode *Load,
bool AArch64TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
return false;
- uint64_t NumBits1 = Ty1->getPrimitiveSizeInBits().getFixedSize();
- uint64_t NumBits2 = Ty2->getPrimitiveSizeInBits().getFixedSize();
+ uint64_t NumBits1 = Ty1->getPrimitiveSizeInBits().getFixedValue();
+ uint64_t NumBits2 = Ty2->getPrimitiveSizeInBits().getFixedValue();
return NumBits1 > NumBits2;
}
bool AArch64TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
@@ -13777,7 +13777,8 @@ bool AArch64TargetLowering::isExtFreeImpl(const Instruction *Ext) const {
// Get the shift amount based on the scaling factor:
// log2(sizeof(IdxTy)) - log2(8).
uint64_t ShiftAmt =
- countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy).getFixedSize()) - 3;
+ countTrailingZeros(DL.getTypeStoreSizeInBits(IdxTy).getFixedValue()) -
+ 3;
// Is the constant foldable in the shift of the addressing mode?
// I.e., shift amount is between 1 and 4 inclusive.
if (ShiftAmt == 0 || ShiftAmt > 4)
@@ -13813,8 +13814,8 @@ static bool areExtractShuffleVectors(Value *Op1, Value *Op2,
auto areTypesHalfed = [](Value *FullV, Value *HalfV) {
auto *FullTy = FullV->getType();
auto *HalfTy = HalfV->getType();
- return FullTy->getPrimitiveSizeInBits().getFixedSize() ==
- 2 * HalfTy->getPrimitiveSizeInBits().getFixedSize();
+ return FullTy->getPrimitiveSizeInBits().getFixedValue() ==
+ 2 * HalfTy->getPrimitiveSizeInBits().getFixedValue();
};
auto extractHalf = [](Value *FullV, Value *HalfV) {
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
index d7e42205fc2d3..a81079943a7dd 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -7383,8 +7383,8 @@ outliner::OutlinedFunction AArch64InstrInfo::getOutliningCandidateInfo(
getMemOpInfo(MI.getOpcode(), Scale, DummyWidth, MinOffset, MaxOffset);
Offset += 16; // Update the offset to what it would be if we outlined.
- if (Offset < MinOffset * (int64_t)Scale.getFixedSize() ||
- Offset > MaxOffset * (int64_t)Scale.getFixedSize())
+ if (Offset < MinOffset * (int64_t)Scale.getFixedValue() ||
+ Offset > MaxOffset * (int64_t)Scale.getFixedValue())
return false;
// It's in range, so we can outline it.
@@ -7860,7 +7860,7 @@ void AArch64InstrInfo::fixupPostOutline(MachineBasicBlock &MBB) const {
// We've pushed the return address to the stack, so add 16 to the offset.
// This is safe, since we already checked if it would overflow when we
// checked if this instruction was legal to outline.
- int64_t NewImm = (Offset + 16) / (int64_t)Scale.getFixedSize();
+ int64_t NewImm = (Offset + 16) / (int64_t)Scale.getFixedValue();
StackOffsetOperand.setImm(NewImm);
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 9f18159d1d7c7..ce073ce64d48e 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2201,9 +2201,9 @@ InstructionCost AArch64TTIImpl::getArithmeticInstrCost(
if (TLI->isOperationLegalOrCustom(ISD, LT.second) && ST->hasSVE()) {
// SDIV/UDIV operations are lowered using SVE, then we can have less
// costs.
- if (isa<FixedVectorType>(Ty) &&
- cast<FixedVectorType>(Ty)->getPrimitiveSizeInBits().getFixedSize() <
- 128) {
+ if (isa<FixedVectorType>(Ty) && cast<FixedVectorType>(Ty)
+ ->getPrimitiveSizeInBits()
+ .getFixedValue() < 128) {
EVT VT = TLI->getValueType(DL, Ty);
static const CostTblEntry DivTbl[]{
{ISD::SDIV, MVT::v2i8, 5}, {ISD::SDIV, MVT::v4i8, 8},
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index b44cf5f2f45c6..6acd6fb3f5e58 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -21200,7 +21200,7 @@ bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
return false;
assert(VectorTy->isVectorTy() && "VectorTy is not a vector type");
- unsigned BitWidth = VectorTy->getPrimitiveSizeInBits().getFixedSize();
+ unsigned BitWidth = VectorTy->getPrimitiveSizeInBits().getFixedValue();
// We can do a store + vector extract on any vector that fits perfectly in a D
// or Q register.
if (BitWidth == 64 || BitWidth == 128) {
@@ -21720,11 +21720,11 @@ static bool isHomogeneousAggregate(Type *Ty, HABaseType &Base,
case HA_DOUBLE:
return false;
case HA_VECT64:
- return VT->getPrimitiveSizeInBits().getFixedSize() == 64;
+ return VT->getPrimitiveSizeInBits().getFixedValue() == 64;
case HA_VECT128:
- return VT->getPrimitiveSizeInBits().getFixedSize() == 128;
+ return VT->getPrimitiveSizeInBits().getFixedValue() == 128;
case HA_UNKNOWN:
- switch (VT->getPrimitiveSizeInBits().getFixedSize()) {
+ switch (VT->getPrimitiveSizeInBits().getFixedValue()) {
case 64:
Base = HA_VECT64;
return true;
diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
index 07786ea827382..7d26dde8c3425 100644
--- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
@@ -1545,7 +1545,7 @@ InstructionCost ARMTTIImpl::getInterleavedMemoryOpCost(
// vmovn.
if (ST->hasMVEIntegerOps() && Factor == 2 && NumElts / Factor > 2 &&
VecTy->isIntOrIntVectorTy() &&
- DL.getTypeSizeInBits(SubVecTy).getFixedSize() <= 64)
+ DL.getTypeSizeInBits(SubVecTy).getFixedValue() <= 64)
return 2 * BaseCost;
}
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
index 6089c865cedfc..67e0723f0906c 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.cpp
@@ -189,11 +189,11 @@ InstructionCost HexagonTTIImpl::getMemoryOpCost(unsigned Opcode, Type *Src,
if (Src->isVectorTy()) {
VectorType *VecTy = cast<VectorType>(Src);
- unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedSize();
+ unsigned VecWidth = VecTy->getPrimitiveSizeInBits().getFixedValue();
if (isHVXVectorType(VecTy)) {
unsigned RegWidth =
getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
- .getFixedSize();
+ .getFixedValue();
assert(RegWidth && "Non-zero vector register width expected");
// Cost of HVX loads.
if (VecWidth % RegWidth == 0)
diff --git a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
index 76653f3bd7a4c..05fa6c42aaf31 100644
--- a/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ b/llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -1392,8 +1392,8 @@ bool MSP430TargetLowering::isTruncateFree(Type *Ty1,
if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
return false;
- return (Ty1->getPrimitiveSizeInBits().getFixedSize() >
- Ty2->getPrimitiveSizeInBits().getFixedSize());
+ return (Ty1->getPrimitiveSizeInBits().getFixedValue() >
+ Ty2->getPrimitiveSizeInBits().getFixedValue());
}
bool MSP430TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index 521bd6ac06657..5d1fc69b24e89 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -3983,7 +3983,7 @@ MipsTargetLowering::getSingleConstraintMatchWeight(
break;
case 'f': // FPU or MSA register
if (Subtarget.hasMSA() && type->isVectorTy() &&
- type->getPrimitiveSizeInBits().getFixedSize() == 128)
+ type->getPrimitiveSizeInBits().getFixedValue() == 128)
weight = CW_Register;
else if (type->isFloatTy())
weight = CW_Register;
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 166f1b6d73761..cb93d2a8f999c 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1567,9 +1567,9 @@ static void getMaxByValAlign(Type *Ty, Align &MaxAlign, Align MaxMaxAlign) {
return;
if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
if (MaxMaxAlign >= 32 &&
- VTy->getPrimitiveSizeInBits().getFixedSize() >= 256)
+ VTy->getPrimitiveSizeInBits().getFixedValue() >= 256)
MaxAlign = Align(32);
- else if (VTy->getPrimitiveSizeInBits().getFixedSize() >= 128 &&
+ else if (VTy->getPrimitiveSizeInBits().getFixedValue() >= 128 &&
MaxAlign < 16)
MaxAlign = Align(16);
} else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
diff --git a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
index 7896a2f9581a3..de627983b5383 100644
--- a/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
@@ -94,7 +94,7 @@ bool RISCVGatherScatterLowering::isLegalTypeAndAlignment(Type *DataType,
return false;
MaybeAlign MA = cast<ConstantInt>(AlignOp)->getMaybeAlignValue();
- if (MA && MA->value() < DL->getTypeStoreSize(ScalarType).getFixedSize())
+ if (MA && MA->value() < DL->getTypeStoreSize(ScalarType).getFixedValue())
return false;
// FIXME: Let the backend type legalize by splitting/widening?
@@ -365,7 +365,7 @@ RISCVGatherScatterLowering::determineBaseAndStride(GetElementPtrInst *GEP,
if (TS.isScalable())
return std::make_pair(nullptr, nullptr);
- TypeScale = TS.getFixedSize();
+ TypeScale = TS.getFixedValue();
}
// We need to find a vector index to simplify.
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 5df266ba35b5c..badb840cd0f86 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -186,7 +186,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
return false;
if (Alignment <
- DL.getTypeStoreSize(DataType->getScalarType()).getFixedSize())
+ DL.getTypeStoreSize(DataType->getScalarType()).getFixedValue())
return false;
return TLI->isLegalElementTypeForRVV(DataType->getScalarType());
@@ -214,7 +214,7 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
return false;
if (Alignment <
- DL.getTypeStoreSize(DataType->getScalarType()).getFixedSize())
+ DL.getTypeStoreSize(DataType->getScalarType()).getFixedValue())
return false;
return TLI->isLegalElementTypeForRVV(DataType->getScalarType());
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 2d2eb709358f3..4ee91d981a828 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -1022,8 +1022,8 @@ EVT SystemZTargetLowering::getOptimalMemOpType(const MemOp &Op,
bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
return false;
- unsigned FromBits = FromType->getPrimitiveSizeInBits().getFixedSize();
- unsigned ToBits = ToType->getPrimitiveSizeInBits().getFixedSize();
+ unsigned FromBits = FromType->getPrimitiveSizeInBits().getFixedValue();
+ unsigned ToBits = ToType->getPrimitiveSizeInBits().getFixedValue();
return FromBits > ToBits;
}
@@ -2489,8 +2489,8 @@ static void adjustICmpTruncate(SelectionDAG &DAG, const SDLoc &DL,
C.Op1.getOpcode() == ISD::Constant &&
cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
- if (L->getMemoryVT().getStoreSizeInBits().getFixedSize() <=
- C.Op0.getValueSizeInBits().getFixedSize()) {
+ if (L->getMemoryVT().getStoreSizeInBits().getFixedValue() <=
+ C.Op0.getValueSizeInBits().getFixedValue()) {
unsigned Type = L->getExtensionType();
if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
(Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
index d6736319a4048..063515019f5c2 100644
--- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.cpp
@@ -647,8 +647,8 @@ static unsigned getElSizeLog2Diff(Type *Ty0, Type *Ty1) {
unsigned SystemZTTIImpl::
getVectorTruncCost(Type *SrcTy, Type *DstTy) {
assert (SrcTy->isVectorTy() && DstTy->isVectorTy());
- assert(SrcTy->getPrimitiveSizeInBits().getFixedSize() >
- DstTy->getPrimitiveSizeInBits().getFixedSize() &&
+ assert(SrcTy->getPrimitiveSizeInBits().getFixedValue() >
+ DstTy->getPrimitiveSizeInBits().getFixedValue() &&
"Packing must reduce size of vector type.");
assert(cast<FixedVectorType>(SrcTy)->getNumElements() ==
cast<FixedVectorType>(DstTy)->getNumElements() &&
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index a2976a86327d9..30a71c64a95e4 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -2633,7 +2633,7 @@ static void getMaxByValAlign(Type *Ty, Align &MaxAlign) {
if (MaxAlign == 16)
return;
if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
- if (VTy->getPrimitiveSizeInBits().getFixedSize() == 128)
+ if (VTy->getPrimitiveSizeInBits().getFixedValue() == 128)
MaxAlign = Align(16);
} else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
Align EltAlign;
@@ -5060,7 +5060,7 @@ bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags,
return false;
if (VA.getLocVT().getFixedSizeInBits() >
- Arg.getValueSizeInBits().getFixedSize()) {
+ Arg.getValueSizeInBits().getFixedValue()) {
// If the argument location is wider than the argument type, check that any
// extension flags match.
if (Flags.isZExt() != MFI.isObjectZExt(FI) ||
@@ -6520,7 +6520,7 @@ static SDValue insert128BitVector(SDValue Result, SDValue Vec, unsigned IdxVal,
static SDValue widenSubVector(MVT VT, SDValue Vec, bool ZeroNewElements,
const X86Subtarget &Subtarget, SelectionDAG &DAG,
const SDLoc &dl) {
- assert(Vec.getValueSizeInBits().getFixedSize() < VT.getFixedSizeInBits() &&
+ assert(Vec.getValueSizeInBits().getFixedValue() < VT.getFixedSizeInBits() &&
Vec.getValueType().getScalarType() == VT.getScalarType() &&
"Unsupported vector widening type");
SDValue Res = ZeroNewElements ? getZeroVector(VT, Subtarget, DAG, dl)
@@ -8352,7 +8352,7 @@ static bool getFauxShuffleMask(SDValue N, const APInt &DemandedElts,
// Subvector shuffle inputs must not be larger than the subvector.
if (llvm::any_of(SubInputs, [SubVT](SDValue SubInput) {
return SubVT.getFixedSizeInBits() <
- SubInput.getValueSizeInBits().getFixedSize();
+ SubInput.getValueSizeInBits().getFixedValue();
}))
return false;
@@ -40698,7 +40698,7 @@ static SDValue combineTargetShuffle(SDValue N, SelectionDAG &DAG,
for (SDNode *User : Src->uses())
if (User != N.getNode() && User->getOpcode() == X86ISD::VBROADCAST &&
Src == User->getOperand(0) &&
- User->getValueSizeInBits(0).getFixedSize() >
+ User->getValueSizeInBits(0).getFixedValue() >
VT.getFixedSizeInBits()) {
return extractSubVector(SDValue(User, 0), 0, DAG, DL,
VT.getSizeInBits());
@@ -50015,7 +50015,7 @@ static SDValue combineLoad(SDNode *N, SelectionDAG &DAG,
cast<MemIntrinsicSDNode>(User)->getMemoryVT().getSizeInBits() ==
MemVT.getSizeInBits() &&
!User->hasAnyUseOfValue(1) &&
- User->getValueSizeInBits(0).getFixedSize() >
+ User->getValueSizeInBits(0).getFixedValue() >
RegVT.getFixedSizeInBits()) {
SDValue Extract = extractSubVector(SDValue(User, 0), 0, DAG, SDLoc(N),
RegVT.getSizeInBits());
@@ -55246,11 +55246,11 @@ static SDValue combineINSERT_SUBVECTOR(SDNode *N, SelectionDAG &DAG,
SDValue Ins = SubVec.getOperand(0);
if (isNullConstant(Ins.getOperand(2)) &&
ISD::isBuildVectorAllZeros(Ins.getOperand(0).getNode()) &&
- Ins.getOperand(1).getValueSizeInBits().getFixedSize() <=
+ Ins.getOperand(1).getValueSizeInBits().getFixedValue() <=
SubVecVT.getFixedSizeInBits())
- return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT,
- getZeroVector(OpVT, Subtarget, DAG, dl),
- Ins.getOperand(1), N->getOperand(2));
+ return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT,
+ getZeroVector(OpVT, Subtarget, DAG, dl),
+ Ins.getOperand(1), N->getOperand(2));
}
}
@@ -55661,7 +55661,7 @@ static SDValue combineScalarToVector(SDNode *N, SelectionDAG &DAG) {
Src == User->getOperand(0)) {
unsigned SizeInBits = VT.getFixedSizeInBits();
unsigned BroadcastSizeInBits =
- User->getValueSizeInBits(0).getFixedSize();
+ User->getValueSizeInBits(0).getFixedValue();
if (BroadcastSizeInBits == SizeInBits)
return SDValue(User, 0);
if (BroadcastSizeInBits > SizeInBits)
@@ -55958,7 +55958,7 @@ static SDValue combineBROADCAST_LOAD(SDNode *N, SelectionDAG &DAG,
cast<MemIntrinsicSDNode>(User)->getMemoryVT().getSizeInBits() ==
MemVT.getSizeInBits() &&
!User->hasAnyUseOfValue(1) &&
- User->getValueSizeInBits(0).getFixedSize() > VT.getFixedSizeInBits()) {
+ User->getValueSizeInBits(0).getFixedValue() > VT.getFixedSizeInBits()) {
SDValue Extract = extractSubVector(SDValue(User, 0), 0, DAG, SDLoc(N),
VT.getSizeInBits());
Extract = DAG.getBitcast(VT, Extract);
diff --git a/llvm/lib/Target/X86/X86InterleavedAccess.cpp b/llvm/lib/Target/X86/X86InterleavedAccess.cpp
index b3fd18cc96880..df4437397f4ca 100644
--- a/llvm/lib/Target/X86/X86InterleavedAccess.cpp
+++ b/llvm/lib/Target/X86/X86InterleavedAccess.cpp
@@ -215,7 +215,7 @@ void X86InterleavedAccessGroup::decompose(
"VecBaseTy's size must be a multiple of 8");
const Align FirstAlignment = LI->getAlign();
const Align SubsequentAlignment = commonAlignment(
- FirstAlignment, VecBaseTy->getPrimitiveSizeInBits().getFixedSize() / 8);
+ FirstAlignment, VecBaseTy->getPrimitiveSizeInBits().getFixedValue() / 8);
Align Alignment = FirstAlignment;
for (unsigned i = 0; i < NumLoads; i++) {
// TODO: Support inbounds GEP.
diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
index d153fb9c310c1..14f1f83b93ea5 100644
--- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -196,7 +196,7 @@ X86TTIImpl::getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const {
unsigned X86TTIImpl::getLoadStoreVecRegBitWidth(unsigned) const {
return getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
- .getFixedSize();
+ .getFixedValue();
}
unsigned X86TTIImpl::getMaxInterleaveFactor(unsigned VF) {
diff --git a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
index 0cac8f560088c..3371f257074dc 100644
--- a/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
+++ b/llvm/lib/Transforms/Coroutines/CoroFrame.cpp
@@ -678,7 +678,7 @@ void FrameTypeBuilder::addFieldForAllocas(const Function &F,
std::optional<TypeSize> RetSize = A.Alloca->getAllocationSize(DL);
assert(RetSize && "Variable Length Arrays (VLA) are not supported.\n");
assert(!RetSize->isScalable() && "Scalable vectors are not yet supported");
- return RetSize->getFixedSize();
+ return RetSize->getFixedValue();
};
// Put larger allocas in the front. So the larger allocas have higher
// priority to merge, which can save more space potentially. Also each
@@ -1086,7 +1086,7 @@ static void buildFrameDebugInfo(Function &F, coro::Shape &Shape,
Type *Ty = FrameTy->getElementType(Index);
assert(Ty->isSized() && "We can't handle type which is not sized.\n");
- SizeInBits = Layout.getTypeSizeInBits(Ty).getFixedSize();
+ SizeInBits = Layout.getTypeSizeInBits(Ty).getFixedValue();
AlignInBits = OffsetCache[Index].first * 8;
OffsetInBits = OffsetCache[Index].second * 8;
diff --git a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
index 00fd0662fe15c..891e6b09d26e3 100644
--- a/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
+++ b/llvm/lib/Transforms/IPO/AttributorAttributes.cpp
@@ -1346,7 +1346,7 @@ struct AAPointerInfoFloating : public AAPointerInfoImpl {
const DataLayout &DL = A.getDataLayout();
TypeSize AccessSize = DL.getTypeStoreSize(&Ty);
if (!AccessSize.isScalable())
- Size = AccessSize.getFixedSize();
+ Size = AccessSize.getFixedValue();
// Make a strictly ascending list of offsets as required by addAccess()
llvm::sort(Offsets);
diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
index 80b9f08758528..0317a8bcb6bc7 100644
--- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp
+++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
@@ -1382,8 +1382,8 @@ static bool isPointerValueDeadOnEntryToFunction(
// and the number of bits loaded in L is less than or equal to
// the number of bits stored in S.
return DT.dominates(S, L) &&
- DL.getTypeStoreSize(LTy).getFixedSize() <=
- DL.getTypeStoreSize(STy).getFixedSize();
+ DL.getTypeStoreSize(LTy).getFixedValue() <=
+ DL.getTypeStoreSize(STy).getFixedValue();
}))
return false;
}
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
index 1fcc78f8fa9e0..b76be357f3168 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
@@ -282,7 +282,7 @@ Instruction *InstCombinerImpl::foldCmpLoadFromIndexedGlobal(
if (!GEP->isInBounds()) {
Type *IntPtrTy = DL.getIntPtrType(GEP->getType());
unsigned PtrSize = IntPtrTy->getIntegerBitWidth();
- if (Idx->getType()->getPrimitiveSizeInBits().getFixedSize() > PtrSize)
+ if (Idx->getType()->getPrimitiveSizeInBits().getFixedValue() > PtrSize)
Idx = Builder.CreateTrunc(Idx, IntPtrTy);
}
@@ -816,8 +816,8 @@ Instruction *InstCombinerImpl::foldGEPICmp(GEPOperator *GEPLHS, Value *RHS,
Type *LHSIndexTy = LOffset->getType();
Type *RHSIndexTy = ROffset->getType();
if (LHSIndexTy != RHSIndexTy) {
- if (LHSIndexTy->getPrimitiveSizeInBits().getFixedSize() <
- RHSIndexTy->getPrimitiveSizeInBits().getFixedSize()) {
+ if (LHSIndexTy->getPrimitiveSizeInBits().getFixedValue() <
+ RHSIndexTy->getPrimitiveSizeInBits().getFixedValue()) {
ROffset = Builder.CreateTrunc(ROffset, LHSIndexTy);
} else
LOffset = Builder.CreateTrunc(LOffset, RHSIndexTy);
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
index 1b427f3bffe8f..c8226ce2816a4 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
@@ -800,7 +800,7 @@ static bool isObjectSizeLessThanOrEq(Value *V, uint64_t MaxSize,
return false;
// Make sure that, even if the multiplication below would wrap as an
// uint64_t, we still do the right thing.
- if ((CS->getValue().zext(128) * APInt(128, TS.getFixedSize()))
+ if ((CS->getValue().zext(128) * APInt(128, TS.getFixedValue()))
.ugt(MaxSize))
return false;
continue;
@@ -878,7 +878,7 @@ static bool canReplaceGEPIdxWithZero(InstCombinerImpl &IC,
if (!AllocTy || !AllocTy->isSized())
return false;
const DataLayout &DL = IC.getDataLayout();
- uint64_t TyAllocSize = DL.getTypeAllocSize(AllocTy).getFixedSize();
+ uint64_t TyAllocSize = DL.getTypeAllocSize(AllocTy).getFixedValue();
// If there are more indices after the one we might replace with a zero, make
// sure they're all non-negative. If any of them are negative, the overall
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
index 96175119f641c..61e62adbe3273 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineVectorOps.cpp
@@ -2878,7 +2878,7 @@ Instruction *InstCombinerImpl::visitShuffleVectorInst(ShuffleVectorInst &SVI) {
Value *V = LHS;
unsigned MaskElems = Mask.size();
auto *SrcTy = cast<FixedVectorType>(V->getType());
- unsigned VecBitWidth = SrcTy->getPrimitiveSizeInBits().getFixedSize();
+ unsigned VecBitWidth = SrcTy->getPrimitiveSizeInBits().getFixedValue();
unsigned SrcElemBitWidth = DL.getTypeSizeInBits(SrcTy->getElementType());
assert(SrcElemBitWidth && "vector elements must have a bitwidth");
unsigned SrcNumElems = SrcTy->getNumElements();
diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
index d29d5ba667f73..f5b22caa37271 100644
--- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -2463,7 +2463,7 @@ Instruction *InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) {
unsigned AS = GEP.getPointerAddressSpace();
if (GEP.getOperand(1)->getType()->getScalarSizeInBits() ==
DL.getIndexSizeInBits(AS)) {
- uint64_t TyAllocSize = DL.getTypeAllocSize(GEPEltType).getFixedSize();
+ uint64_t TyAllocSize = DL.getTypeAllocSize(GEPEltType).getFixedValue();
bool Matched = false;
uint64_t C;
@@ -2593,8 +2593,9 @@ Instruction *InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) {
if (GEPEltType->isSized() && StrippedPtrEltTy->isSized()) {
// Check that changing the type amounts to dividing the index by a scale
// factor.
- uint64_t ResSize = DL.getTypeAllocSize(GEPEltType).getFixedSize();
- uint64_t SrcSize = DL.getTypeAllocSize(StrippedPtrEltTy).getFixedSize();
+ uint64_t ResSize = DL.getTypeAllocSize(GEPEltType).getFixedValue();
+ uint64_t SrcSize =
+ DL.getTypeAllocSize(StrippedPtrEltTy).getFixedValue();
if (ResSize && SrcSize % ResSize == 0) {
Value *Idx = GEP.getOperand(1);
unsigned BitWidth = Idx->getType()->getPrimitiveSizeInBits();
@@ -2630,10 +2631,10 @@ Instruction *InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) {
StrippedPtrEltTy->isArrayTy()) {
// Check that changing to the array element type amounts to dividing the
// index by a scale factor.
- uint64_t ResSize = DL.getTypeAllocSize(GEPEltType).getFixedSize();
+ uint64_t ResSize = DL.getTypeAllocSize(GEPEltType).getFixedValue();
uint64_t ArrayEltSize =
DL.getTypeAllocSize(StrippedPtrEltTy->getArrayElementType())
- .getFixedSize();
+ .getFixedValue();
if (ResSize && ArrayEltSize % ResSize == 0) {
Value *Idx = GEP.getOperand(1);
unsigned BitWidth = Idx->getType()->getPrimitiveSizeInBits();
diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
index f0e4f8cd4403d..4dd6afe13747e 100644
--- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
+++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp
@@ -1533,7 +1533,7 @@ struct MemorySanitizerVisitor : public InstVisitor<MemorySanitizerVisitor> {
Type *getShadowTyNoVec(Type *ty) {
if (VectorType *vt = dyn_cast<VectorType>(ty))
return IntegerType::get(*MS.C,
- vt->getPrimitiveSizeInBits().getFixedSize());
+ vt->getPrimitiveSizeInBits().getFixedValue());
return ty;
}
diff --git a/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp b/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
index 43f0658d45dfa..23a88c3cfba22 100644
--- a/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
+++ b/llvm/lib/Transforms/Instrumentation/SanitizerCoverage.cpp
@@ -722,7 +722,7 @@ GlobalVariable *ModuleSanitizerCoverage::CreateFunctionLocalArrayInSection(
if (auto Comdat = getOrCreateFunctionComdat(F, TargetTriple))
Array->setComdat(Comdat);
Array->setSection(getSectionName(Section));
- Array->setAlignment(Align(DL->getTypeStoreSize(Ty).getFixedSize()));
+ Array->setAlignment(Align(DL->getTypeStoreSize(Ty).getFixedValue()));
// sancov_pcs parallels the other metadata section(s). Optimizers (e.g.
// GlobalOpt/ConstantMerge) may not discard sancov_pcs and the other
diff --git a/llvm/lib/Transforms/Scalar/LICM.cpp b/llvm/lib/Transforms/Scalar/LICM.cpp
index f7d36a49d6d25..cb8d5f1b187e9 100644
--- a/llvm/lib/Transforms/Scalar/LICM.cpp
+++ b/llvm/lib/Transforms/Scalar/LICM.cpp
@@ -1097,7 +1097,7 @@ static bool isLoadInvariantInLoop(LoadInst *LI, DominatorTree *DT,
// in bits. Also, the invariant.start should dominate the load, and we
// should not hoist the load out of a loop that contains this dominating
// invariant.start.
- if (LocSizeInBits.getFixedSize() <= InvariantSizeInBits &&
+ if (LocSizeInBits.getFixedValue() <= InvariantSizeInBits &&
DT->properlyDominates(II->getParent(), CurLoop->getHeader()))
return true;
}
diff --git a/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp b/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
index 2dc97a49f367a..e2493c5aa83d6 100644
--- a/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopIdiomRecognize.cpp
@@ -496,8 +496,8 @@ LoopIdiomRecognize::isLegalStore(StoreInst *SI) {
// When storing out scalable vectors we bail out for now, since the code
// below currently only works for constant strides.
TypeSize SizeInBits = DL->getTypeSizeInBits(StoredVal->getType());
- if (SizeInBits.isScalable() || (SizeInBits.getFixedSize() & 7) ||
- (SizeInBits.getFixedSize() >> 32) != 0)
+ if (SizeInBits.isScalable() || (SizeInBits.getFixedValue() & 7) ||
+ (SizeInBits.getFixedValue() >> 32) != 0)
return LegalStoreKind::None;
// See if the pointer expression is an AddRec like {base,+,1} on the current
@@ -1296,7 +1296,7 @@ class MemmoveVerifier {
// Ensure that LoadBasePtr is after StoreBasePtr or before StoreBasePtr
// for negative stride. LoadBasePtr shouldn't overlap with StoreBasePtr.
int64_t LoadSize =
- DL.getTypeSizeInBits(TheLoad.getType()).getFixedSize() / 8;
+ DL.getTypeSizeInBits(TheLoad.getType()).getFixedValue() / 8;
if (BP1 != BP2 || LoadSize != int64_t(StoreSize))
return false;
if ((!IsNegStride && LoadOff < StoreOff + int64_t(StoreSize)) ||
diff --git a/llvm/lib/Transforms/Scalar/LoopPredication.cpp b/llvm/lib/Transforms/Scalar/LoopPredication.cpp
index 0492ed5cdb1ca..578b399363678 100644
--- a/llvm/lib/Transforms/Scalar/LoopPredication.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopPredication.cpp
@@ -454,8 +454,8 @@ static bool isSafeToTruncateWideIVType(const DataLayout &DL,
Type *RangeCheckType) {
if (!EnableIVTruncation)
return false;
- assert(DL.getTypeSizeInBits(LatchCheck.IV->getType()).getFixedSize() >
- DL.getTypeSizeInBits(RangeCheckType).getFixedSize() &&
+ assert(DL.getTypeSizeInBits(LatchCheck.IV->getType()).getFixedValue() >
+ DL.getTypeSizeInBits(RangeCheckType).getFixedValue() &&
"Expected latch check IV type to be larger than range check operand "
"type!");
// The start and end values of the IV should be known. This is to guarantee
@@ -475,7 +475,7 @@ static bool isSafeToTruncateWideIVType(const DataLayout &DL,
// guarantees that truncating the latch check to RangeCheckType is a safe
// operation.
auto RangeCheckTypeBitSize =
- DL.getTypeSizeInBits(RangeCheckType).getFixedSize();
+ DL.getTypeSizeInBits(RangeCheckType).getFixedValue();
return Start->getAPInt().getActiveBits() < RangeCheckTypeBitSize &&
Limit->getAPInt().getActiveBits() < RangeCheckTypeBitSize;
}
@@ -492,8 +492,8 @@ static std::optional<LoopICmp> generateLoopLatchCheck(const DataLayout &DL,
if (RangeCheckType == LatchType)
return LatchCheck;
// For now, bail out if latch type is narrower than range type.
- if (DL.getTypeSizeInBits(LatchType).getFixedSize() <
- DL.getTypeSizeInBits(RangeCheckType).getFixedSize())
+ if (DL.getTypeSizeInBits(LatchType).getFixedValue() <
+ DL.getTypeSizeInBits(RangeCheckType).getFixedValue())
return std::nullopt;
if (!isSafeToTruncateWideIVType(DL, SE, LatchCheck, RangeCheckType))
return std::nullopt;
diff --git a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
index 0a0827a933fb4..08c6406f0a30e 100644
--- a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
+++ b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
@@ -459,10 +459,10 @@ class LowerMatrixIntrinsics {
/// Return the estimated number of vector ops required for an operation on
/// \p VT * N.
unsigned getNumOps(Type *ST, unsigned N) {
- return std::ceil((ST->getPrimitiveSizeInBits() * N).getFixedSize() /
+ return std::ceil((ST->getPrimitiveSizeInBits() * N).getFixedValue() /
double(TTI.getRegisterBitWidth(
TargetTransformInfo::RGK_FixedWidthVector)
- .getFixedSize()));
+ .getFixedValue()));
}
/// Return the set of vectors that a matrix value is lowered to.
@@ -1260,8 +1260,8 @@ class LowerMatrixIntrinsics {
bool IsScalarMatrixTransposed, FastMathFlags FMF) {
const unsigned VF = std::max<unsigned>(
TTI.getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
- .getFixedSize() /
- Result.getElementType()->getPrimitiveSizeInBits().getFixedSize(),
+ .getFixedValue() /
+ Result.getElementType()->getPrimitiveSizeInBits().getFixedValue(),
1U);
unsigned R = Result.getNumRows();
unsigned C = Result.getNumColumns();
@@ -1439,8 +1439,8 @@ class LowerMatrixIntrinsics {
const unsigned VF = std::max<unsigned>(
TTI.getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
- .getFixedSize() /
- EltType->getPrimitiveSizeInBits().getFixedSize(),
+ .getFixedValue() /
+ EltType->getPrimitiveSizeInBits().getFixedValue(),
1U);
// Cost model for tiling
diff --git a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
index 4c63c6fed1c2e..80865782adcd5 100644
--- a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
+++ b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
@@ -176,8 +176,8 @@ class MemsetRanges {
void addStore(int64_t OffsetFromFirst, StoreInst *SI) {
TypeSize StoreSize = DL.getTypeStoreSize(SI->getOperand(0)->getType());
assert(!StoreSize.isScalable() && "Can't track scalable-typed stores");
- addRange(OffsetFromFirst, StoreSize.getFixedSize(), SI->getPointerOperand(),
- SI->getAlign(), SI);
+ addRange(OffsetFromFirst, StoreSize.getFixedValue(),
+ SI->getPointerOperand(), SI->getAlign(), SI);
}
void addMemSet(int64_t OffsetFromFirst, MemSetInst *MSI) {
diff --git a/llvm/lib/Transforms/Scalar/NaryReassociate.cpp b/llvm/lib/Transforms/Scalar/NaryReassociate.cpp
index ab6c28c803795..19bee4fa38795 100644
--- a/llvm/lib/Transforms/Scalar/NaryReassociate.cpp
+++ b/llvm/lib/Transforms/Scalar/NaryReassociate.cpp
@@ -403,8 +403,9 @@ NaryReassociatePass::tryReassociateGEPAtIndex(GetElementPtrInst *GEP,
// Replace the I-th index with LHS.
IndexExprs[I] = SE->getSCEV(LHS);
if (isKnownNonNegative(LHS, *DL, 0, AC, GEP, DT) &&
- DL->getTypeSizeInBits(LHS->getType()).getFixedSize() <
- DL->getTypeSizeInBits(GEP->getOperand(I)->getType()).getFixedSize()) {
+ DL->getTypeSizeInBits(LHS->getType()).getFixedValue() <
+ DL->getTypeSizeInBits(GEP->getOperand(I)->getType())
+ .getFixedValue()) {
// Zero-extend LHS if it is non-negative. InstCombine canonicalizes sext to
// zext if the source operand is proved non-negative. We should do that
// consistently so that CandidateExpr more likely appears before. See
diff --git a/llvm/lib/Transforms/Scalar/SROA.cpp b/llvm/lib/Transforms/Scalar/SROA.cpp
index ed346fc1f430e..58f3a84a2879b 100644
--- a/llvm/lib/Transforms/Scalar/SROA.cpp
+++ b/llvm/lib/Transforms/Scalar/SROA.cpp
@@ -763,7 +763,7 @@ class AllocaSlices::SliceBuilder : public PtrUseVisitor<SliceBuilder> {
public:
SliceBuilder(const DataLayout &DL, AllocaInst &AI, AllocaSlices &AS)
: PtrUseVisitor<SliceBuilder>(DL),
- AllocSize(DL.getTypeAllocSize(AI.getAllocatedType()).getFixedSize()),
+ AllocSize(DL.getTypeAllocSize(AI.getAllocatedType()).getFixedValue()),
AS(AS) {}
private:
@@ -856,7 +856,7 @@ class AllocaSlices::SliceBuilder : public PtrUseVisitor<SliceBuilder> {
GEPOffset +=
Index *
APInt(Offset.getBitWidth(),
- DL.getTypeAllocSize(GTI.getIndexedType()).getFixedSize());
+ DL.getTypeAllocSize(GTI.getIndexedType()).getFixedValue());
}
// If this index has computed an intermediate pointer which is not
@@ -891,7 +891,7 @@ class AllocaSlices::SliceBuilder : public PtrUseVisitor<SliceBuilder> {
if (isa<ScalableVectorType>(LI.getType()))
return PI.setAborted(&LI);
- uint64_t Size = DL.getTypeStoreSize(LI.getType()).getFixedSize();
+ uint64_t Size = DL.getTypeStoreSize(LI.getType()).getFixedValue();
return handleLoadOrStore(LI.getType(), LI, Offset, Size, LI.isVolatile());
}
@@ -905,7 +905,7 @@ class AllocaSlices::SliceBuilder : public PtrUseVisitor<SliceBuilder> {
if (isa<ScalableVectorType>(ValOp->getType()))
return PI.setAborted(&SI);
- uint64_t Size = DL.getTypeStoreSize(ValOp->getType()).getFixedSize();
+ uint64_t Size = DL.getTypeStoreSize(ValOp->getType()).getFixedValue();
// If this memory access can be shown to *statically* extend outside the
// bounds of the allocation, it's behavior is undefined, so simply
@@ -1061,16 +1061,16 @@ class AllocaSlices::SliceBuilder : public PtrUseVisitor<SliceBuilder> {
std::tie(UsedI, I) = Uses.pop_back_val();
if (LoadInst *LI = dyn_cast<LoadInst>(I)) {
- Size = std::max(Size,
- DL.getTypeStoreSize(LI->getType()).getFixedSize());
+ Size =
+ std::max(Size, DL.getTypeStoreSize(LI->getType()).getFixedValue());
continue;
}
if (StoreInst *SI = dyn_cast<StoreInst>(I)) {
Value *Op = SI->getOperand(0);
if (Op == UsedI)
return SI;
- Size = std::max(Size,
- DL.getTypeStoreSize(Op->getType()).getFixedSize());
+ Size =
+ std::max(Size, DL.getTypeStoreSize(Op->getType()).getFixedValue());
continue;
}
@@ -1331,7 +1331,8 @@ static bool isSafePHIToSpeculate(PHINode &PN) {
if (!LoadType)
return false;
- APInt LoadSize = APInt(APWidth, DL.getTypeStoreSize(LoadType).getFixedSize());
+ APInt LoadSize =
+ APInt(APWidth, DL.getTypeStoreSize(LoadType).getFixedValue());
// We can only transform this if it is safe to push the loads into the
// predecessor blocks. The only thing to watch out for is that we can't put
@@ -1912,8 +1913,8 @@ static bool canConvertValue(const DataLayout &DL, Type *OldTy, Type *NewTy) {
return false;
}
- if (DL.getTypeSizeInBits(NewTy).getFixedSize() !=
- DL.getTypeSizeInBits(OldTy).getFixedSize())
+ if (DL.getTypeSizeInBits(NewTy).getFixedValue() !=
+ DL.getTypeSizeInBits(OldTy).getFixedValue())
return false;
if (!NewTy->isSingleValueType() || !OldTy->isSingleValueType())
return false;
@@ -2091,13 +2092,13 @@ static bool isVectorPromotionViableForSlice(Partition &P, const Slice &S,
static bool checkVectorTypeForPromotion(Partition &P, VectorType *VTy,
const DataLayout &DL) {
uint64_t ElementSize =
- DL.getTypeSizeInBits(VTy->getElementType()).getFixedSize();
+ DL.getTypeSizeInBits(VTy->getElementType()).getFixedValue();
// While the definition of LLVM vectors is bitpacked, we don't support sizes
// that aren't byte sized.
if (ElementSize % 8)
return false;
- assert((DL.getTypeSizeInBits(VTy).getFixedSize() % 8) == 0 &&
+ assert((DL.getTypeSizeInBits(VTy).getFixedValue() % 8) == 0 &&
"vector size not a multiple of element size?");
ElementSize /= 8;
@@ -2135,8 +2136,8 @@ static VectorType *isVectorPromotionViable(Partition &P, const DataLayout &DL) {
// Return if bitcast to vectors is
diff erent for total size in bits.
if (!CandidateTys.empty()) {
VectorType *V = CandidateTys[0];
- if (DL.getTypeSizeInBits(VTy).getFixedSize() !=
- DL.getTypeSizeInBits(V).getFixedSize()) {
+ if (DL.getTypeSizeInBits(VTy).getFixedValue() !=
+ DL.getTypeSizeInBits(V).getFixedValue()) {
CandidateTys.clear();
return;
}
@@ -2196,8 +2197,8 @@ static VectorType *isVectorPromotionViable(Partition &P, const DataLayout &DL) {
// they're all integer vectors. We sort by ascending number of elements.
auto RankVectorTypes = [&DL](VectorType *RHSTy, VectorType *LHSTy) {
(void)DL;
- assert(DL.getTypeSizeInBits(RHSTy).getFixedSize() ==
- DL.getTypeSizeInBits(LHSTy).getFixedSize() &&
+ assert(DL.getTypeSizeInBits(RHSTy).getFixedValue() ==
+ DL.getTypeSizeInBits(LHSTy).getFixedValue() &&
"Cannot have vector types of
diff erent sizes!");
assert(RHSTy->getElementType()->isIntegerTy() &&
"All non-integer types eliminated!");
@@ -2247,7 +2248,7 @@ static bool isIntegerWideningViableForSlice(const Slice &S,
Type *AllocaTy,
const DataLayout &DL,
bool &WholeAllocaOp) {
- uint64_t Size = DL.getTypeStoreSize(AllocaTy).getFixedSize();
+ uint64_t Size = DL.getTypeStoreSize(AllocaTy).getFixedValue();
uint64_t RelBegin = S.beginOffset() - AllocBeginOffset;
uint64_t RelEnd = S.endOffset() - AllocBeginOffset;
@@ -2272,7 +2273,7 @@ static bool isIntegerWideningViableForSlice(const Slice &S,
if (LI->isVolatile())
return false;
// We can't handle loads that extend past the allocated memory.
- if (DL.getTypeStoreSize(LI->getType()).getFixedSize() > Size)
+ if (DL.getTypeStoreSize(LI->getType()).getFixedValue() > Size)
return false;
// So far, AllocaSliceRewriter does not support widening split slice tails
// in rewriteIntegerLoad.
@@ -2284,7 +2285,7 @@ static bool isIntegerWideningViableForSlice(const Slice &S,
if (!isa<VectorType>(LI->getType()) && RelBegin == 0 && RelEnd == Size)
WholeAllocaOp = true;
if (IntegerType *ITy = dyn_cast<IntegerType>(LI->getType())) {
- if (ITy->getBitWidth() < DL.getTypeStoreSizeInBits(ITy).getFixedSize())
+ if (ITy->getBitWidth() < DL.getTypeStoreSizeInBits(ITy).getFixedValue())
return false;
} else if (RelBegin != 0 || RelEnd != Size ||
!canConvertValue(DL, AllocaTy, LI->getType())) {
@@ -2297,7 +2298,7 @@ static bool isIntegerWideningViableForSlice(const Slice &S,
if (SI->isVolatile())
return false;
// We can't handle stores that extend past the allocated memory.
- if (DL.getTypeStoreSize(ValueTy).getFixedSize() > Size)
+ if (DL.getTypeStoreSize(ValueTy).getFixedValue() > Size)
return false;
// So far, AllocaSliceRewriter does not support widening split slice tails
// in rewriteIntegerStore.
@@ -2309,7 +2310,7 @@ static bool isIntegerWideningViableForSlice(const Slice &S,
if (!isa<VectorType>(ValueTy) && RelBegin == 0 && RelEnd == Size)
WholeAllocaOp = true;
if (IntegerType *ITy = dyn_cast<IntegerType>(ValueTy)) {
- if (ITy->getBitWidth() < DL.getTypeStoreSizeInBits(ITy).getFixedSize())
+ if (ITy->getBitWidth() < DL.getTypeStoreSizeInBits(ITy).getFixedValue())
return false;
} else if (RelBegin != 0 || RelEnd != Size ||
!canConvertValue(DL, ValueTy, AllocaTy)) {
@@ -2337,13 +2338,13 @@ static bool isIntegerWideningViableForSlice(const Slice &S,
/// promote the resulting alloca.
static bool isIntegerWideningViable(Partition &P, Type *AllocaTy,
const DataLayout &DL) {
- uint64_t SizeInBits = DL.getTypeSizeInBits(AllocaTy).getFixedSize();
+ uint64_t SizeInBits = DL.getTypeSizeInBits(AllocaTy).getFixedValue();
// Don't create integer types larger than the maximum bitwidth.
if (SizeInBits > IntegerType::MAX_INT_BITS)
return false;
// Don't try to handle allocas with bit-padding.
- if (SizeInBits != DL.getTypeStoreSizeInBits(AllocaTy).getFixedSize())
+ if (SizeInBits != DL.getTypeStoreSizeInBits(AllocaTy).getFixedValue())
return false;
// We need to ensure that an integer type with the appropriate bitwidth can
@@ -2381,13 +2382,13 @@ static Value *extractInteger(const DataLayout &DL, IRBuilderTy &IRB, Value *V,
const Twine &Name) {
LLVM_DEBUG(dbgs() << " start: " << *V << "\n");
IntegerType *IntTy = cast<IntegerType>(V->getType());
- assert(DL.getTypeStoreSize(Ty).getFixedSize() + Offset <=
- DL.getTypeStoreSize(IntTy).getFixedSize() &&
+ assert(DL.getTypeStoreSize(Ty).getFixedValue() + Offset <=
+ DL.getTypeStoreSize(IntTy).getFixedValue() &&
"Element extends past full value");
uint64_t ShAmt = 8 * Offset;
if (DL.isBigEndian())
- ShAmt = 8 * (DL.getTypeStoreSize(IntTy).getFixedSize() -
- DL.getTypeStoreSize(Ty).getFixedSize() - Offset);
+ ShAmt = 8 * (DL.getTypeStoreSize(IntTy).getFixedValue() -
+ DL.getTypeStoreSize(Ty).getFixedValue() - Offset);
if (ShAmt) {
V = IRB.CreateLShr(V, ShAmt, Name + ".shift");
LLVM_DEBUG(dbgs() << " shifted: " << *V << "\n");
@@ -2412,13 +2413,13 @@ static Value *insertInteger(const DataLayout &DL, IRBuilderTy &IRB, Value *Old,
V = IRB.CreateZExt(V, IntTy, Name + ".ext");
LLVM_DEBUG(dbgs() << " extended: " << *V << "\n");
}
- assert(DL.getTypeStoreSize(Ty).getFixedSize() + Offset <=
- DL.getTypeStoreSize(IntTy).getFixedSize() &&
+ assert(DL.getTypeStoreSize(Ty).getFixedValue() + Offset <=
+ DL.getTypeStoreSize(IntTy).getFixedValue() &&
"Element store outside of alloca store");
uint64_t ShAmt = 8 * Offset;
if (DL.isBigEndian())
- ShAmt = 8 * (DL.getTypeStoreSize(IntTy).getFixedSize() -
- DL.getTypeStoreSize(Ty).getFixedSize() - Offset);
+ ShAmt = 8 * (DL.getTypeStoreSize(IntTy).getFixedValue() -
+ DL.getTypeStoreSize(Ty).getFixedValue() - Offset);
if (ShAmt) {
V = IRB.CreateShl(V, ShAmt, Name + ".shift");
LLVM_DEBUG(dbgs() << " shifted: " << *V << "\n");
@@ -2594,16 +2595,16 @@ class llvm::sroa::AllocaSliceRewriter
IsIntegerPromotable
? Type::getIntNTy(NewAI.getContext(),
DL.getTypeSizeInBits(NewAI.getAllocatedType())
- .getFixedSize())
+ .getFixedValue())
: nullptr),
VecTy(PromotableVecTy),
ElementTy(VecTy ? VecTy->getElementType() : nullptr),
- ElementSize(VecTy ? DL.getTypeSizeInBits(ElementTy).getFixedSize() / 8
+ ElementSize(VecTy ? DL.getTypeSizeInBits(ElementTy).getFixedValue() / 8
: 0),
PHIUsers(PHIUsers), SelectUsers(SelectUsers),
IRB(NewAI.getContext(), ConstantFolder()) {
if (VecTy) {
- assert((DL.getTypeSizeInBits(ElementTy).getFixedSize() % 8) == 0 &&
+ assert((DL.getTypeSizeInBits(ElementTy).getFixedValue() % 8) == 0 &&
"Only multiple-of-8 sized vector elements are viable");
++NumVectorized;
}
@@ -2772,7 +2773,7 @@ class llvm::sroa::AllocaSliceRewriter
Type *TargetTy = IsSplit ? Type::getIntNTy(LI.getContext(), SliceSize * 8)
: LI.getType();
const bool IsLoadPastEnd =
- DL.getTypeStoreSize(TargetTy).getFixedSize() > SliceSize;
+ DL.getTypeStoreSize(TargetTy).getFixedValue() > SliceSize;
bool IsPtrAdjusted = false;
Value *V;
if (VecTy) {
@@ -2844,7 +2845,7 @@ class llvm::sroa::AllocaSliceRewriter
assert(!LI.isVolatile());
assert(LI.getType()->isIntegerTy() &&
"Only integer type loads and stores are split");
- assert(SliceSize < DL.getTypeStoreSize(LI.getType()).getFixedSize() &&
+ assert(SliceSize < DL.getTypeStoreSize(LI.getType()).getFixedValue() &&
"Split load isn't smaller than original load");
assert(DL.typeSizeEqualsStoreSize(LI.getType()) &&
"Non-byte-multiple bit width");
@@ -2912,7 +2913,7 @@ class llvm::sroa::AllocaSliceRewriter
bool rewriteIntegerStore(Value *V, StoreInst &SI, AAMDNodes AATags) {
assert(IntTy && "We cannot extract an integer from the alloca");
assert(!SI.isVolatile());
- if (DL.getTypeSizeInBits(V->getType()).getFixedSize() !=
+ if (DL.getTypeSizeInBits(V->getType()).getFixedValue() !=
IntTy->getBitWidth()) {
Value *Old = IRB.CreateAlignedLoad(NewAI.getAllocatedType(), &NewAI,
NewAI.getAlign(), "oldload");
@@ -2950,7 +2951,7 @@ class llvm::sroa::AllocaSliceRewriter
if (AllocaInst *AI = dyn_cast<AllocaInst>(V->stripInBoundsOffsets()))
Pass.PostPromotionWorklist.insert(AI);
- if (SliceSize < DL.getTypeStoreSize(V->getType()).getFixedSize()) {
+ if (SliceSize < DL.getTypeStoreSize(V->getType()).getFixedValue()) {
assert(!SI.isVolatile());
assert(V->getType()->isIntegerTy() &&
"Only integer type loads and stores are split");
@@ -2967,7 +2968,7 @@ class llvm::sroa::AllocaSliceRewriter
return rewriteIntegerStore(V, SI, AATags);
const bool IsStorePastEnd =
- DL.getTypeStoreSize(V->getType()).getFixedSize() > SliceSize;
+ DL.getTypeStoreSize(V->getType()).getFixedValue() > SliceSize;
StoreInst *NewSI;
if (NewBeginOffset == NewAllocaBeginOffset &&
NewEndOffset == NewAllocaEndOffset &&
@@ -3094,7 +3095,7 @@ class llvm::sroa::AllocaSliceRewriter
auto *Int8Ty = IntegerType::getInt8Ty(NewAI.getContext());
auto *SrcTy = FixedVectorType::get(Int8Ty, Len);
return canConvertValue(DL, SrcTy, AllocaTy) &&
- DL.isLegalInteger(DL.getTypeSizeInBits(ScalarTy).getFixedSize());
+ DL.isLegalInteger(DL.getTypeSizeInBits(ScalarTy).getFixedValue());
}();
// If this doesn't map cleanly onto the alloca type, and that type isn't
@@ -3134,7 +3135,7 @@ class llvm::sroa::AllocaSliceRewriter
"Too many elements!");
Value *Splat = getIntegerSplat(
- II.getValue(), DL.getTypeSizeInBits(ElementTy).getFixedSize() / 8);
+ II.getValue(), DL.getTypeSizeInBits(ElementTy).getFixedValue() / 8);
Splat = convertValue(DL, IRB, Splat, ElementTy);
if (NumElements > 1)
Splat = getVectorSplat(Splat, NumElements);
@@ -3168,7 +3169,7 @@ class llvm::sroa::AllocaSliceRewriter
assert(NewEndOffset == NewAllocaEndOffset);
V = getIntegerSplat(II.getValue(),
- DL.getTypeSizeInBits(ScalarTy).getFixedSize() / 8);
+ DL.getTypeSizeInBits(ScalarTy).getFixedValue() / 8);
if (VectorType *AllocaVecTy = dyn_cast<VectorType>(AllocaTy))
V = getVectorSplat(
V, cast<FixedVectorType>(AllocaVecTy)->getNumElements());
@@ -3244,7 +3245,7 @@ class llvm::sroa::AllocaSliceRewriter
!VecTy && !IntTy &&
(BeginOffset > NewAllocaBeginOffset || EndOffset < NewAllocaEndOffset ||
SliceSize !=
- DL.getTypeStoreSize(NewAI.getAllocatedType()).getFixedSize() ||
+ DL.getTypeStoreSize(NewAI.getAllocatedType()).getFixedValue() ||
!NewAI.getAllocatedType()->isSingleValueType());
// If we're just going to emit a memcpy, the alloca hasn't changed, and the
@@ -3949,8 +3950,8 @@ static Type *stripAggregateTypeWrapping(const DataLayout &DL, Type *Ty) {
if (Ty->isSingleValueType())
return Ty;
- uint64_t AllocSize = DL.getTypeAllocSize(Ty).getFixedSize();
- uint64_t TypeSize = DL.getTypeSizeInBits(Ty).getFixedSize();
+ uint64_t AllocSize = DL.getTypeAllocSize(Ty).getFixedValue();
+ uint64_t TypeSize = DL.getTypeSizeInBits(Ty).getFixedValue();
Type *InnerTy;
if (ArrayType *ArrTy = dyn_cast<ArrayType>(Ty)) {
@@ -3963,8 +3964,8 @@ static Type *stripAggregateTypeWrapping(const DataLayout &DL, Type *Ty) {
return Ty;
}
- if (AllocSize > DL.getTypeAllocSize(InnerTy).getFixedSize() ||
- TypeSize > DL.getTypeSizeInBits(InnerTy).getFixedSize())
+ if (AllocSize > DL.getTypeAllocSize(InnerTy).getFixedValue() ||
+ TypeSize > DL.getTypeSizeInBits(InnerTy).getFixedValue())
return Ty;
return stripAggregateTypeWrapping(DL, InnerTy);
@@ -3985,10 +3986,10 @@ static Type *stripAggregateTypeWrapping(const DataLayout &DL, Type *Ty) {
/// return a type if necessary.
static Type *getTypePartition(const DataLayout &DL, Type *Ty, uint64_t Offset,
uint64_t Size) {
- if (Offset == 0 && DL.getTypeAllocSize(Ty).getFixedSize() == Size)
+ if (Offset == 0 && DL.getTypeAllocSize(Ty).getFixedValue() == Size)
return stripAggregateTypeWrapping(DL, Ty);
- if (Offset > DL.getTypeAllocSize(Ty).getFixedSize() ||
- (DL.getTypeAllocSize(Ty).getFixedSize() - Offset) < Size)
+ if (Offset > DL.getTypeAllocSize(Ty).getFixedValue() ||
+ (DL.getTypeAllocSize(Ty).getFixedValue() - Offset) < Size)
return nullptr;
if (isa<ArrayType>(Ty) || isa<VectorType>(Ty)) {
@@ -4004,7 +4005,7 @@ static Type *getTypePartition(const DataLayout &DL, Type *Ty, uint64_t Offset,
ElementTy = VT->getElementType();
TyNumElements = VT->getNumElements();
}
- uint64_t ElementSize = DL.getTypeAllocSize(ElementTy).getFixedSize();
+ uint64_t ElementSize = DL.getTypeAllocSize(ElementTy).getFixedValue();
uint64_t NumSkippedElements = Offset / ElementSize;
if (NumSkippedElements >= TyNumElements)
return nullptr;
@@ -4044,7 +4045,7 @@ static Type *getTypePartition(const DataLayout &DL, Type *Ty, uint64_t Offset,
Offset -= SL->getElementOffset(Index);
Type *ElementTy = STy->getElementType(Index);
- uint64_t ElementSize = DL.getTypeAllocSize(ElementTy).getFixedSize();
+ uint64_t ElementSize = DL.getTypeAllocSize(ElementTy).getFixedValue();
if (Offset >= ElementSize)
return nullptr; // The offset points into alignment padding.
@@ -4604,7 +4605,7 @@ AllocaInst *SROAPass::rewritePartition(AllocaInst &AI, AllocaSlices &AS,
findCommonType(P.begin(), P.end(), P.endOffset());
// Do all uses operate on the same type?
if (CommonUseTy.first)
- if (DL.getTypeAllocSize(CommonUseTy.first).getFixedSize() >= P.size()) {
+ if (DL.getTypeAllocSize(CommonUseTy.first).getFixedValue() >= P.size()) {
SliceTy = CommonUseTy.first;
SliceVecTy = dyn_cast<VectorType>(SliceTy);
}
@@ -4616,7 +4617,7 @@ AllocaInst *SROAPass::rewritePartition(AllocaInst &AI, AllocaSlices &AS,
// If still not, can we use the largest bitwidth integer type used?
if (!SliceTy && CommonUseTy.second)
- if (DL.getTypeAllocSize(CommonUseTy.second).getFixedSize() >= P.size()) {
+ if (DL.getTypeAllocSize(CommonUseTy.second).getFixedValue() >= P.size()) {
SliceTy = CommonUseTy.second;
SliceVecTy = dyn_cast<VectorType>(SliceTy);
}
@@ -4639,7 +4640,7 @@ AllocaInst *SROAPass::rewritePartition(AllocaInst &AI, AllocaSlices &AS,
if (!SliceTy)
SliceTy = ArrayType::get(Type::getInt8Ty(*C), P.size());
- assert(DL.getTypeAllocSize(SliceTy).getFixedSize() >= P.size());
+ assert(DL.getTypeAllocSize(SliceTy).getFixedValue() >= P.size());
bool IsIntegerPromotable = isIntegerWideningViable(P, SliceTy, DL);
@@ -4795,7 +4796,7 @@ bool SROAPass::splitAlloca(AllocaInst &AI, AllocaSlices &AS) {
bool IsSorted = true;
uint64_t AllocaSize =
- DL.getTypeAllocSize(AI.getAllocatedType()).getFixedSize();
+ DL.getTypeAllocSize(AI.getAllocatedType()).getFixedValue();
const uint64_t MaxBitVectorSize = 1024;
if (AllocaSize <= MaxBitVectorSize) {
// If a byte boundary is included in any load or store, a slice starting or
@@ -4860,7 +4861,7 @@ bool SROAPass::splitAlloca(AllocaInst &AI, AllocaSlices &AS) {
if (NewAI != &AI) {
uint64_t SizeOfByte = 8;
uint64_t AllocaSize =
- DL.getTypeSizeInBits(NewAI->getAllocatedType()).getFixedSize();
+ DL.getTypeSizeInBits(NewAI->getAllocatedType()).getFixedValue();
// Don't include any padding.
uint64_t Size = std::min(AllocaSize, P.size() * SizeOfByte);
Fragments.push_back(Fragment(NewAI, P.beginOffset() * SizeOfByte, Size));
@@ -4881,7 +4882,7 @@ bool SROAPass::splitAlloca(AllocaInst &AI, AllocaSlices &AS) {
auto *Expr = DbgDeclare->getExpression();
DIBuilder DIB(*AI.getModule(), /*AllowUnresolved*/ false);
uint64_t AllocaSize =
- DL.getTypeSizeInBits(AI.getAllocatedType()).getFixedSize();
+ DL.getTypeSizeInBits(AI.getAllocatedType()).getFixedValue();
for (auto Fragment : Fragments) {
// Create a fragment expression describing the new partition or reuse AI's
// expression if there is only one partition.
@@ -5002,7 +5003,7 @@ SROAPass::runOnAlloca(AllocaInst &AI) {
// Skip alloca forms that this analysis can't handle.
auto *AT = AI.getAllocatedType();
if (AI.isArrayAllocation() || !AT->isSized() || isa<ScalableVectorType>(AT) ||
- DL.getTypeAllocSize(AT).getFixedSize() == 0)
+ DL.getTypeAllocSize(AT).getFixedValue() == 0)
return {Changed, CFGChanged};
// First, split any FCA loads and stores touching this alloca to promote
diff --git a/llvm/lib/Transforms/Utils/FunctionComparator.cpp b/llvm/lib/Transforms/Utils/FunctionComparator.cpp
index 53bac207251eb..6e93de540cf15 100644
--- a/llvm/lib/Transforms/Utils/FunctionComparator.cpp
+++ b/llvm/lib/Transforms/Utils/FunctionComparator.cpp
@@ -241,9 +241,9 @@ int FunctionComparator::cmpConstants(const Constant *L,
unsigned TyRWidth = 0;
if (auto *VecTyL = dyn_cast<VectorType>(TyL))
- TyLWidth = VecTyL->getPrimitiveSizeInBits().getFixedSize();
+ TyLWidth = VecTyL->getPrimitiveSizeInBits().getFixedValue();
if (auto *VecTyR = dyn_cast<VectorType>(TyR))
- TyRWidth = VecTyR->getPrimitiveSizeInBits().getFixedSize();
+ TyRWidth = VecTyR->getPrimitiveSizeInBits().getFixedValue();
if (TyLWidth != TyRWidth)
return cmpNumbers(TyLWidth, TyRWidth);
diff --git a/llvm/lib/Transforms/Utils/InlineFunction.cpp b/llvm/lib/Transforms/Utils/InlineFunction.cpp
index 6aaaa33cebdec..e80d388fa124b 100644
--- a/llvm/lib/Transforms/Utils/InlineFunction.cpp
+++ b/llvm/lib/Transforms/Utils/InlineFunction.cpp
@@ -2504,7 +2504,7 @@ llvm::InlineResult llvm::InlineFunction(CallBase &CB, InlineFunctionInfo &IFI,
if (!AllocaTypeSize.isScalable() &&
AllocaArraySize != std::numeric_limits<uint64_t>::max() &&
std::numeric_limits<uint64_t>::max() / AllocaArraySize >=
- AllocaTypeSize.getFixedSize()) {
+ AllocaTypeSize.getFixedValue()) {
AllocaSize = ConstantInt::get(Type::getInt64Ty(AI->getContext()),
AllocaArraySize * AllocaTypeSize);
}
diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp
index e43a3fbaefdbe..cd9ee04f852b0 100644
--- a/llvm/lib/Transforms/Utils/Local.cpp
+++ b/llvm/lib/Transforms/Utils/Local.cpp
@@ -1496,7 +1496,7 @@ static bool valueCoversEntireFragment(Type *ValTy, DbgVariableIntrinsic *DII) {
if (std::optional<uint64_t> FragmentSize = DII->getFragmentSizeInBits()) {
assert(!ValueSize.isScalable() &&
"Fragments don't work on scalable types.");
- return ValueSize.getFixedSize() >= *FragmentSize;
+ return ValueSize.getFixedValue() >= *FragmentSize;
}
// We can't always calculate the size of the DI variable (e.g. if it is a
// VLA). Try to use the size of the alloca that the dbg intrinsic describes
diff --git a/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp b/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
index 9341291a72d2d..899928c085c66 100644
--- a/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
+++ b/llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
@@ -309,7 +309,7 @@ void MemoryOpRemark::visitVariable(const Value *V,
SmallVectorImpl<VariableInfo> &Result) {
if (auto *GV = dyn_cast<GlobalVariable>(V)) {
auto *Ty = GV->getValueType();
- uint64_t Size = DL.getTypeSizeInBits(Ty).getFixedSize();
+ uint64_t Size = DL.getTypeSizeInBits(Ty).getFixedValue();
VariableInfo Var{nameOrNone(GV), Size};
if (!Var.isEmpty())
Result.push_back(std::move(Var));
@@ -343,7 +343,7 @@ void MemoryOpRemark::visitVariable(const Value *V,
// If not, get it from the alloca.
std::optional<TypeSize> TySize = AI->getAllocationSize(DL);
std::optional<uint64_t> Size =
- TySize ? std::optional(TySize->getFixedSize()) : std::nullopt;
+ TySize ? std::optional(TySize->getFixedValue()) : std::nullopt;
VariableInfo Var{nameOrNone(AI), Size};
if (!Var.isEmpty())
Result.push_back(std::move(Var));
diff --git a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
index 80b0a20724311..c027638f9958e 100644
--- a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
+++ b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
@@ -1906,8 +1906,8 @@ SCEVExpander::replaceCongruentIVs(Loop *L, const DominatorTree *DT,
// Put pointers at the back and make sure pointer < pointer = false.
if (!LHS->getType()->isIntegerTy() || !RHS->getType()->isIntegerTy())
return RHS->getType()->isIntegerTy() && !LHS->getType()->isIntegerTy();
- return RHS->getType()->getPrimitiveSizeInBits().getFixedSize() <
- LHS->getType()->getPrimitiveSizeInBits().getFixedSize();
+ return RHS->getType()->getPrimitiveSizeInBits().getFixedValue() <
+ LHS->getType()->getPrimitiveSizeInBits().getFixedValue();
});
unsigned NumElim = 0;
diff --git a/llvm/lib/Transforms/Utils/VNCoercion.cpp b/llvm/lib/Transforms/Utils/VNCoercion.cpp
index d179b8b5fcccc..f295a7e312b6d 100644
--- a/llvm/lib/Transforms/Utils/VNCoercion.cpp
+++ b/llvm/lib/Transforms/Utils/VNCoercion.cpp
@@ -28,14 +28,14 @@ bool canCoerceMustAliasedValueToLoad(Value *StoredVal, Type *LoadTy,
isFirstClassAggregateOrScalableType(StoredTy))
return false;
- uint64_t StoreSize = DL.getTypeSizeInBits(StoredTy).getFixedSize();
+ uint64_t StoreSize = DL.getTypeSizeInBits(StoredTy).getFixedValue();
// The store size must be byte-aligned to support future type casts.
if (llvm::alignTo(StoreSize, 8) != StoreSize)
return false;
// The store has to be at least as big as the load.
- if (StoreSize < DL.getTypeSizeInBits(LoadTy).getFixedSize())
+ if (StoreSize < DL.getTypeSizeInBits(LoadTy).getFixedValue())
return false;
bool StoredNI = DL.isNonIntegralPointerType(StoredTy->getScalarType());
@@ -58,7 +58,7 @@ bool canCoerceMustAliasedValueToLoad(Value *StoredVal, Type *LoadTy,
// The implementation below uses inttoptr for vectors of unequal size; we
// can't allow this for non integral pointers. We could teach it to extract
// exact subvectors if desired.
- if (StoredNI && StoreSize != DL.getTypeSizeInBits(LoadTy).getFixedSize())
+ if (StoredNI && StoreSize != DL.getTypeSizeInBits(LoadTy).getFixedValue())
return false;
if (StoredTy->isTargetExtTy() || LoadTy->isTargetExtTy())
@@ -84,8 +84,8 @@ Value *coerceAvailableValueToLoadType(Value *StoredVal, Type *LoadedTy,
// If this is already the right type, just return it.
Type *StoredValTy = StoredVal->getType();
- uint64_t StoredValSize = DL.getTypeSizeInBits(StoredValTy).getFixedSize();
- uint64_t LoadedValSize = DL.getTypeSizeInBits(LoadedTy).getFixedSize();
+ uint64_t StoredValSize = DL.getTypeSizeInBits(StoredValTy).getFixedValue();
+ uint64_t LoadedValSize = DL.getTypeSizeInBits(LoadedTy).getFixedValue();
// If the store and reload are the same size, we can always reuse it.
if (StoredValSize == LoadedValSize) {
@@ -137,8 +137,8 @@ Value *coerceAvailableValueToLoadType(Value *StoredVal, Type *LoadedTy,
// If this is a big-endian system, we need to shift the value down to the low
// bits so that a truncate will work.
if (DL.isBigEndian()) {
- uint64_t ShiftAmt = DL.getTypeStoreSizeInBits(StoredValTy).getFixedSize() -
- DL.getTypeStoreSizeInBits(LoadedTy).getFixedSize();
+ uint64_t ShiftAmt = DL.getTypeStoreSizeInBits(StoredValTy).getFixedValue() -
+ DL.getTypeStoreSizeInBits(LoadedTy).getFixedValue();
StoredVal = Helper.CreateLShr(
StoredVal, ConstantInt::get(StoredVal->getType(), ShiftAmt));
}
@@ -186,7 +186,7 @@ static int analyzeLoadFromClobberingWrite(Type *LoadTy, Value *LoadPtr,
if (StoreBase != LoadBase)
return -1;
- uint64_t LoadSize = DL.getTypeSizeInBits(LoadTy).getFixedSize();
+ uint64_t LoadSize = DL.getTypeSizeInBits(LoadTy).getFixedValue();
if ((WriteSizeInBits & 7) | (LoadSize & 7))
return -1;
@@ -221,7 +221,7 @@ int analyzeLoadFromClobberingStore(Type *LoadTy, Value *LoadPtr,
Value *StorePtr = DepSI->getPointerOperand();
uint64_t StoreSize =
- DL.getTypeSizeInBits(DepSI->getValueOperand()->getType()).getFixedSize();
+ DL.getTypeSizeInBits(DepSI->getValueOperand()->getType()).getFixedValue();
return analyzeLoadFromClobberingWrite(LoadTy, LoadPtr, StorePtr, StoreSize,
DL);
}
@@ -324,7 +324,7 @@ int analyzeLoadFromClobberingLoad(Type *LoadTy, Value *LoadPtr, LoadInst *DepLI,
return -1;
Value *DepPtr = DepLI->getPointerOperand();
- uint64_t DepSize = DL.getTypeSizeInBits(DepLI->getType()).getFixedSize();
+ uint64_t DepSize = DL.getTypeSizeInBits(DepLI->getType()).getFixedValue();
int R = analyzeLoadFromClobberingWrite(LoadTy, LoadPtr, DepPtr, DepSize, DL);
if (R != -1)
return R;
@@ -334,7 +334,7 @@ int analyzeLoadFromClobberingLoad(Type *LoadTy, Value *LoadPtr, LoadInst *DepLI,
int64_t LoadOffs = 0;
const Value *LoadBase =
GetPointerBaseWithConstantOffset(LoadPtr, LoadOffs, DL);
- unsigned LoadSize = DL.getTypeStoreSize(LoadTy).getFixedSize();
+ unsigned LoadSize = DL.getTypeStoreSize(LoadTy).getFixedValue();
unsigned Size =
getLoadLoadClobberFullWidthSize(LoadBase, LoadOffs, LoadSize, DepLI);
@@ -411,8 +411,8 @@ static Value *getStoreValueForLoadHelper(Value *SrcVal, unsigned Offset,
}
uint64_t StoreSize =
- (DL.getTypeSizeInBits(SrcVal->getType()).getFixedSize() + 7) / 8;
- uint64_t LoadSize = (DL.getTypeSizeInBits(LoadTy).getFixedSize() + 7) / 8;
+ (DL.getTypeSizeInBits(SrcVal->getType()).getFixedValue() + 7) / 8;
+ uint64_t LoadSize = (DL.getTypeSizeInBits(LoadTy).getFixedValue() + 7) / 8;
// Compute which bits of the stored value are being used by the load. Convert
// to an integer type to start with.
if (SrcVal->getType()->isPtrOrPtrVectorTy())
@@ -465,8 +465,8 @@ Value *getLoadValueForLoad(LoadInst *SrcVal, unsigned Offset, Type *LoadTy,
// If Offset+LoadTy exceeds the size of SrcVal, then we must be wanting to
// widen SrcVal out to a larger load.
unsigned SrcValStoreSize =
- DL.getTypeStoreSize(SrcVal->getType()).getFixedSize();
- unsigned LoadSize = DL.getTypeStoreSize(LoadTy).getFixedSize();
+ DL.getTypeStoreSize(SrcVal->getType()).getFixedValue();
+ unsigned LoadSize = DL.getTypeStoreSize(LoadTy).getFixedValue();
if (Offset + LoadSize > SrcValStoreSize) {
assert(SrcVal->isSimple() && "Cannot widen volatile/atomic load!");
assert(SrcVal->getType()->isIntegerTy() && "Can't widen non-integer load");
@@ -510,8 +510,8 @@ Value *getLoadValueForLoad(LoadInst *SrcVal, unsigned Offset, Type *LoadTy,
Constant *getConstantLoadValueForLoad(Constant *SrcVal, unsigned Offset,
Type *LoadTy, const DataLayout &DL) {
unsigned SrcValStoreSize =
- DL.getTypeStoreSize(SrcVal->getType()).getFixedSize();
- unsigned LoadSize = DL.getTypeStoreSize(LoadTy).getFixedSize();
+ DL.getTypeStoreSize(SrcVal->getType()).getFixedValue();
+ unsigned LoadSize = DL.getTypeStoreSize(LoadTy).getFixedValue();
if (Offset + LoadSize > SrcValStoreSize)
return nullptr;
return getConstantStoreValueForLoad(SrcVal, Offset, LoadTy, DL);
@@ -523,7 +523,7 @@ Value *getMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset,
Type *LoadTy, Instruction *InsertPt,
const DataLayout &DL) {
LLVMContext &Ctx = LoadTy->getContext();
- uint64_t LoadSize = DL.getTypeSizeInBits(LoadTy).getFixedSize() / 8;
+ uint64_t LoadSize = DL.getTypeSizeInBits(LoadTy).getFixedValue() / 8;
IRBuilder<> Builder(InsertPt);
// We know that this method is only called when the mem transfer fully
@@ -569,7 +569,7 @@ Value *getMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset,
Constant *getConstantMemInstValueForLoad(MemIntrinsic *SrcInst, unsigned Offset,
Type *LoadTy, const DataLayout &DL) {
LLVMContext &Ctx = LoadTy->getContext();
- uint64_t LoadSize = DL.getTypeSizeInBits(LoadTy).getFixedSize() / 8;
+ uint64_t LoadSize = DL.getTypeSizeInBits(LoadTy).getFixedValue() / 8;
// We know that this method is only called when the mem transfer fully
// provides the bits for the load.
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index 5aab3d17b1d4a..c6b80e7721117 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -5616,9 +5616,9 @@ LoopVectorizationCostModel::getSmallestAndWidestTypes() {
} else {
for (Type *T : ElementTypesInLoop) {
MinWidth = std::min<unsigned>(
- MinWidth, DL.getTypeSizeInBits(T->getScalarType()).getFixedSize());
+ MinWidth, DL.getTypeSizeInBits(T->getScalarType()).getFixedValue());
MaxWidth = std::max<unsigned>(
- MaxWidth, DL.getTypeSizeInBits(T->getScalarType()).getFixedSize());
+ MaxWidth, DL.getTypeSizeInBits(T->getScalarType()).getFixedValue());
}
}
return {MinWidth, MaxWidth};
@@ -7459,7 +7459,7 @@ LoopVectorizationPlanner::planInVPlanNativePath(ElementCount UserVF) {
if (UserVF.isZero()) {
VF = ElementCount::getFixed(determineVPlanVF(
TTI->getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
- .getFixedSize(),
+ .getFixedValue(),
CM));
LLVM_DEBUG(dbgs() << "LV: VPlan computed VF " << VF << ".\n");
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 746a2488c6996..df46773a908f1 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -991,7 +991,7 @@ class BoUpSLP {
else
MaxVecRegSize =
TTI->getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector)
- .getFixedSize();
+ .getFixedValue();
if (MinVectorRegSizeOption.getNumOccurrences())
MinVecRegSize = MinVectorRegSizeOption;
diff --git a/llvm/unittests/AsmParser/AsmParserTest.cpp b/llvm/unittests/AsmParser/AsmParserTest.cpp
index 2747d17bb8069..23a0dedd78c02 100644
--- a/llvm/unittests/AsmParser/AsmParserTest.cpp
+++ b/llvm/unittests/AsmParser/AsmParserTest.cpp
@@ -232,7 +232,7 @@ TEST(AsmParserTest, TypeWithSlotMappingParsing) {
// Check the details of the vector.
auto *VT = cast<FixedVectorType>(Ty);
ASSERT_TRUE(VT->getNumElements() == 5);
- ASSERT_TRUE(VT->getPrimitiveSizeInBits().getFixedSize() == 160);
+ ASSERT_TRUE(VT->getPrimitiveSizeInBits().getFixedValue() == 160);
Ty = VT->getElementType();
ASSERT_TRUE(Ty->isIntegerTy());
ASSERT_TRUE(Ty->getPrimitiveSizeInBits() == 32);
@@ -347,7 +347,7 @@ TEST(AsmParserTest, TypeAtBeginningWithSlotMappingParsing) {
// Check the details of the vector.
auto *VT = cast<FixedVectorType>(Ty);
ASSERT_TRUE(VT->getNumElements() == 5);
- ASSERT_TRUE(VT->getPrimitiveSizeInBits().getFixedSize() == 160);
+ ASSERT_TRUE(VT->getPrimitiveSizeInBits().getFixedValue() == 160);
Ty = VT->getElementType();
ASSERT_TRUE(Ty->isIntegerTy());
ASSERT_TRUE(Ty->getPrimitiveSizeInBits() == 32);
diff --git a/llvm/unittests/IR/VectorTypesTest.cpp b/llvm/unittests/IR/VectorTypesTest.cpp
index d58bab55766d0..7ba143eeeeb81 100644
--- a/llvm/unittests/IR/VectorTypesTest.cpp
+++ b/llvm/unittests/IR/VectorTypesTest.cpp
@@ -290,18 +290,18 @@ TEST(VectorTypesTest, FixedLenComparisons) {
EXPECT_EQ(V2I32Len.getKnownMinValue(), 64U);
EXPECT_FALSE(V2I32Len.isScalable());
- EXPECT_LT(V2Int32Ty->getPrimitiveSizeInBits().getFixedSize(),
- V4Int32Ty->getPrimitiveSizeInBits().getFixedSize());
- EXPECT_GT(V2Int64Ty->getPrimitiveSizeInBits().getFixedSize(),
- V2Int32Ty->getPrimitiveSizeInBits().getFixedSize());
+ EXPECT_LT(V2Int32Ty->getPrimitiveSizeInBits().getFixedValue(),
+ V4Int32Ty->getPrimitiveSizeInBits().getFixedValue());
+ EXPECT_GT(V2Int64Ty->getPrimitiveSizeInBits().getFixedValue(),
+ V2Int32Ty->getPrimitiveSizeInBits().getFixedValue());
EXPECT_EQ(V4Int32Ty->getPrimitiveSizeInBits(),
V2Int64Ty->getPrimitiveSizeInBits());
EXPECT_NE(V2Int32Ty->getPrimitiveSizeInBits(),
V2Int64Ty->getPrimitiveSizeInBits());
// Check that a fixed-only comparison works for fixed size vectors.
- EXPECT_EQ(V2Int64Ty->getPrimitiveSizeInBits().getFixedSize(),
- V4Int32Ty->getPrimitiveSizeInBits().getFixedSize());
+ EXPECT_EQ(V2Int64Ty->getPrimitiveSizeInBits().getFixedValue(),
+ V4Int32Ty->getPrimitiveSizeInBits().getFixedValue());
// Check the DataLayout interfaces.
EXPECT_EQ(DL.getTypeSizeInBits(V2Int64Ty), DL.getTypeSizeInBits(V4Int32Ty));
diff --git a/llvm/unittests/Support/TypeSizeTest.cpp b/llvm/unittests/Support/TypeSizeTest.cpp
index c64134b8e165b..2850705d39f69 100644
--- a/llvm/unittests/Support/TypeSizeTest.cpp
+++ b/llvm/unittests/Support/TypeSizeTest.cpp
@@ -63,9 +63,9 @@ constexpr TypeSize TSFixed0 = TypeSize::Fixed(0);
constexpr TypeSize TSFixed1 = TypeSize::Fixed(1);
constexpr TypeSize TSFixed32 = TypeSize::Fixed(32);
-static_assert(TSFixed0.getFixedSize() == 0);
-static_assert(TSFixed1.getFixedSize() == 1);
-static_assert(TSFixed32.getFixedSize() == 32);
+static_assert(TSFixed0.getFixedValue() == 0);
+static_assert(TSFixed1.getFixedValue() == 1);
+static_assert(TSFixed32.getFixedValue() == 32);
static_assert(TSFixed32.getKnownMinValue() == 32);
static_assert(TypeSize::Scalable(32).getKnownMinValue() == 32);
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index 46b2ac44bd925..c79c79948a80d 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -187,8 +187,8 @@ class LLTCodeGen {
std::make_tuple(
Other.Ty.isScalable(),
Other.Ty.getSizeInBits().getKnownMinValue())
- : Ty.getSizeInBits().getFixedSize() <
- Other.Ty.getSizeInBits().getFixedSize();
+ : Ty.getSizeInBits().getFixedValue() <
+ Other.Ty.getSizeInBits().getFixedValue();
}
bool operator==(const LLTCodeGen &B) const { return Ty == B.Ty; }
More information about the llvm-commits
mailing list