[PATCH] D141485: [X86] Add schedule module for SapphireRapids
Haohai, Wen via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jan 11 05:46:46 PST 2023
HaohaiWen added a comment.
Instruction's scheduling info in this model comes from many sources.
Priority of source is (dsc order)
1. 4th Generation Intel® Xeon® Scalable Processor Family (based on Sapphire Rapids Architecture) Instruction Throughput and Latency in https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html
2. Alderlake-P data from uops.info
3. Current SkylakeServerModel.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D141485/new/
https://reviews.llvm.org/D141485
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