[llvm] 78c5747 - [AMDGPU] Use MCInstrDesc::getSize. NFC.

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2023-01-11T13:22:38Z
New Revision: 78c5747bd6a59270d07aa4441a721dd671e730be

URL: https://github.com/llvm/llvm-project/commit/78c5747bd6a59270d07aa4441a721dd671e730be
DIFF: https://github.com/llvm/llvm-project/commit/78c5747bd6a59270d07aa4441a721dd671e730be.diff

LOG: [AMDGPU] Use MCInstrDesc::getSize. NFC.

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp

Removed: 
    


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diff  --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
index be4b477547ad3..2592584b89c6b 100644
--- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -599,7 +599,7 @@ bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
     LLVM_DEBUG(dbgs() << "  try: " << OrigMI);
 
     auto OrigOp = OrigMI.getOpcode();
-    assert((TII->get(OrigOp).Size != 4 || !AMDGPU::isTrue16Inst(OrigOp)) &&
+    assert((TII->get(OrigOp).getSize() != 4 || !AMDGPU::isTrue16Inst(OrigOp)) &&
            "There should not be e32 True16 instructions pre-RA");
     if (OrigOp == AMDGPU::REG_SEQUENCE) {
       Register FwdReg = OrigMI.getOperand(0).getReg();