[PATCH] D141479: [RISCV] Generate march string from target features

[Wang Pengcheng via Phabricator via llvm-commits]

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As what has been mentioned in D137517 <https://reviews.llvm.org/D137517>, this patch is to simplify
processors definitions in RISCV.td. We don't have to specify march
string since we can generate it from target features.

The disadvantage is that the generated march string is too tedious.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141479

Files:
  llvm/lib/Target/RISCV/RISCV.td
  llvm/utils/TableGen/RISCVTargetDefEmitter.cpp

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