[PATCH] D140782: [RISCV] Teach lowerCTLZ_CTTZ_ZERO_UNDEF to handle conversion i32/i64 vectors to f32 vectors.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3592
+                            DAG.getConstant(ShiftAmt, DL, IntVT));
+  // Restore back to original type. Truncation after SRL is to generate snrl.
+  if (IntVT.bitsLT(VT))
----------------
craig.topper wrote:
> snrl ->vnsrl?
This wasn't addressed


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3594
+  if (IntVT.bitsLT(VT))
+    Exp = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Exp);
+  else if (IntVT.bitsGT(VT))
----------------
craig.topper wrote:
> ANY_EXTEND is allowed to place random values into the extra bits. I think you want ZERO_EXTEND here.
This wasn't addressed


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Comment at: llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll:1092
+; CHECK-F-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
+; CHECK-F-NEXT:    vmset.m v0
+; CHECK-F-NEXT:    fsrmi a0, 1
----------------
Any idea where this vmset came from?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140782/new/

https://reviews.llvm.org/D140782