[PATCH] D141359: [AArch64] Only enable `foldCSELOfCSEl` DAG combine when x != y

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

LGTM Thanks



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:20024
 
+// When x != y
 // (CSEL l r EQ (CMP (CSEL x y cc2 cond) x)) => (CSEL l r cc2 cond)
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These could be combined into the "Where x and y are constants" line.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:20057-20060
+  // If one of the constant is opaque constant,
+  // x,y sdnode is still different but the real value
+  // maybe the same. So check APInt here to make sure
+  // the code is correct.
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This comment could be formatted to flow better.


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Comment at: llvm/test/CodeGen/AArch64/pr59902.ll:4
+
+; this used to miscompile because foldCSELOfCSEL function
+; doesn't check const x != y
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this -> This


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https://reviews.llvm.org/D141359