[PATCH] D140782: [RISCV] Teach lowerCTLZ_CTTZ_ZERO_UNDEF to handle conversion i32/i64 vectors to f32 vectors.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3544
+    [[fallthrough]];
+  case 64:
+    // Fraction of f32 is not able to present each i32/i64 value.
----------------
I think we should use f64 for i64 if it is available. That avoids a narrowing conversion.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3546
+    // Fraction of f32 is not able to present each i32/i64 value.
+    // Use RTZ to avoid rounding influencing exponent of FLoatVal.
+    UseRTZ = true;
----------------
FLoatVal -> FloatVal


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3592
+                            DAG.getConstant(ShiftAmt, DL, IntVT));
+  // Restore back to original type. Truncation after SRL is to generate snrl.
+  if (IntVT.bitsLT(VT))
----------------
snrl ->vnsrl?


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3594
+  if (IntVT.bitsLT(VT))
+    Exp = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Exp);
+  else if (IntVT.bitsGT(VT))
----------------
ANY_EXTEND is allowed to place random values into the extra bits. I think you want ZERO_EXTEND here.


================
Comment at: llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll:1523
+; RV64I-NEXT:    ret
   %a = call <vscale x 2 x i64> @llvm.cttz.nxv2i64(<vscale x 2 x i64> %va, i1 false)
   ret <vscale x 2 x i64> %a
----------------
Missing CHECK-F and CHECK-D here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140782/new/

https://reviews.llvm.org/D140782