[PATCH] D141408: [CodeGen] Introduce a generic MEMBARRIER instruction [mostly-nfc]

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
reames added reviewers: craig.topper, arsenm, asb, jrtc27, lenary.
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reames requested review of this revision.
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This is a follow up to D141317 <https://reviews.llvm.org/D141317> which extends the common code to include a target independent pseudo instruction.  This is an alternative to (subset of) D92842 <https://reviews.llvm.org/D92842> which tries to be as close to NFC as possible.

A couple things to call out for reviewers.

1. I couldn't find a way to do tablegen matching for a generic SDAG node to a generic MI.  I hacked this up, but surely there's something obvious I'm missing here?  If not, I can cleanup the hacky code; I just didn't bother in the hopes there was a table gen based approach I'd missed.

2. The test change in X86 is because we loose the scheduling information on the instruction.  However, I think this was actually a bug in x86 since no instruction was emitted for a MEMBARRIER.  Concluding that a meta instruction has latency just seems wrong?

3. More generally, is there anything specifically I need to do around scheduling info for the generic instruction?  I'm unfamiliar with that part of our system.

4. I intentionally left some parts of D92842 <https://reviews.llvm.org/D92842> out.  Specifically, several of the changes in the X86 code (data independence and outlining) appear functional, and likely worthy of their own review.  Additionally, I'm not handling ARM/AArch64 at all.  Those targets need the ordering whereas none of the others do.  I want to get this in and tested before retrofitting in ordering to support those targets.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141408

Files:
  llvm/include/llvm/Support/TargetOpcodes.def
  llvm/include/llvm/Target/Target.td
  llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
  llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
  llvm/lib/Target/SystemZ/SystemZInstrInfo.td
  llvm/lib/Target/SystemZ/SystemZLongBranch.cpp
  llvm/lib/Target/VE/VEInstrInfo.td
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86MCInstLower.cpp
  llvm/lib/Target/XCore/XCoreInstrInfo.td
  llvm/test/CodeGen/X86/atomic-idempotent.ll
  llvm/unittests/MIR/MachineMetadata.cpp

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