[PATCH] D141406: [AArch64] Codegen for FEAT_LSE128

[Sam Elliott via Phabricator via llvm-commits]

lenary added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:21997
+  assert(ISDOpcode != ISD::ATOMIC_LOAD_CLR &&
+         "ATOMIC_LOAD_AND should be lowered to LDCLRP directly");
+  assert(ISDOpcode != ISD::ATOMIC_LOAD_ADD && "There is no 128 bit LDADD");
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I am also confused about this assert message.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:22176
+    assert(N->getValueType(0) != MVT::i128 &&
+           "128-bit ATOMIC_LOAD_AND should be lowered directly to LDCLRP");
+    break;
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The message here doesn't correspond to the case?


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Comment at: llvm/test/CodeGen/AArch64/Atomics/aarch64-atomic-store-lse128.ll:119
 define dso_local void @store_atomic_i128_aligned_unordered(i128 %value, ptr %ptr) {
-; -O0-LABEL: store_atomic_i128_aligned_unordered:
-; -O0:    casp x0, x1, x2, x3, [x8]
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I thought we tested O0 because of globalisel, but here both O0 and O1 are updated, despite not having changed globalisel. Why?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141406/new/

https://reviews.llvm.org/D141406