[PATCH] D141405: [ARM] Accept two-register form of vnmul

[Jirui Wu via Phabricator via llvm-commits]

JiruiWu created this revision.
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The previous vnmul only accepts three registers. It should accept either
two or three registers as vmul does.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141405

Files:
  llvm/lib/Target/ARM/ARMInstrVFP.td
  llvm/test/MC/ARM/simple-fp-encoding.s
  llvm/test/MC/Disassembler/ARM/fp-encoding.txt


Index: llvm/test/MC/Disassembler/ARM/fp-encoding.txt
===================================================================
--- llvm/test/MC/Disassembler/ARM/fp-encoding.txt
+++ llvm/test/MC/Disassembler/ARM/fp-encoding.txt
@@ -27,6 +27,9 @@
 0xe0 0x0b 0x61 0xee
 # CHECK: vnmul.f64       d16, d17, d16
 
+0x41 0x0b 0x20 0xee
+# CHECK: vnmul.f64       d0, d0, d1
+
 0xc0 0x0a 0x20 0xee
 # CHECK: vnmul.f32       s0, s1, s0
 
Index: llvm/test/MC/ARM/simple-fp-encoding.s
===================================================================
--- llvm/test/MC/ARM/simple-fp-encoding.s
+++ llvm/test/MC/ARM/simple-fp-encoding.s
@@ -34,9 +34,11 @@
 
         vnmul.f64       d16, d17, d16
         vnmul.f32       s0, s1, s0
+        vnmul.f64       d0, d1
 
 @ CHECK: vnmul.f64 d16, d17, d16     @ encoding: [0xe0,0x0b,0x61,0xee]
 @ CHECK: vnmul.f32 s0, s1, s0        @ encoding: [0xc0,0x0a,0x20,0xee]
+@ CHECK: vnmul.f64 d0, d0, d1        @ encoding: [0x41,0x0b,0x20,0xee]
 
         vcmp.f64       d17, d16
         vcmp.f32       s1, s0
Index: llvm/lib/Target/ARM/ARMInstrVFP.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrVFP.td
+++ llvm/lib/Target/ARM/ARMInstrVFP.td
@@ -496,12 +496,14 @@
                   [(set (f16 HPR:$Sd), (fmul (f16 HPR:$Sn), (f16 HPR:$Sm)))]>,
              Sched<[WriteFPMUL32, ReadFPMUL, ReadFPMUL]>;
 
+let TwoOperandAliasConstraint = "$Dn = $Dd" in
 def VNMULD : ADbI<0b11100, 0b10, 1, 0,
                   (outs DPR:$Dd), (ins DPR:$Dn, DPR:$Dm),
                   IIC_fpMUL64, "vnmul", ".f64\t$Dd, $Dn, $Dm",
                   [(set DPR:$Dd, (fneg (fmul DPR:$Dn, (f64 DPR:$Dm))))]>,
              Sched<[WriteFPMUL64, ReadFPMUL, ReadFPMUL]>;
 
+let TwoOperandAliasConstraint = "$Sn = $Sd" in
 def VNMULS : ASbI<0b11100, 0b10, 1, 0,
                   (outs SPR:$Sd), (ins SPR:$Sn, SPR:$Sm),
                   IIC_fpMUL32, "vnmul", ".f32\t$Sd, $Sn, $Sm",
@@ -512,6 +514,7 @@
   let D = VFPNeonA8Domain;
 }
 
+let TwoOperandAliasConstraint = "$Sn = $Sd" in
 def VNMULH : AHbI<0b11100, 0b10, 1, 0,
                   (outs HPR:$Sd), (ins HPR:$Sn, HPR:$Sm),
                   IIC_fpMUL16, "vnmul", ".f16\t$Sd, $Sn, $Sm",


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