[PATCH] D141395: [RISCV][ISelLowering] Fix select lowering issue
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Tue Jan 10 08:48:22 PST 2023
dybv-sc created this revision.
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Fix bug that leads to some pseudo instructions not being lowered.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D141395
Files:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/float-select-verify.ll
Index: llvm/test/CodeGen/RISCV/float-select-verify.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/float-select-verify.ll
@@ -0,0 +1,22 @@
+; NOTE: This check verifies that ISelLowering does not skip instructions while lowering select sequence.
+; NOTE: opt would exit with fatal error if pseudo instruction skipped.
+; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s
+
+define dso_local void @buz(i1 %pred, float %a, float %b) {
+entry:
+ %0 = call float @llvm.round.f32(float %a)
+ %cond = select i1 %pred, float %0, float %a
+ %1 = call float @llvm.round.f32(float %b)
+ %cond2 = select i1 %pred, float %1, float %b
+ %conv = fptosi float %cond2 to i64
+ call void @bar(float %cond)
+ call void @foo(i64 %conv)
+ ret void
+}
+
+declare void @foo(i64)
+
+declare void @bar(float)
+
+declare float @llvm.round.f32(float)
+
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -11189,6 +11189,7 @@
// multiple selects with the exact same condition (same LHS, RHS and CC).
// The selects may be interleaved with other instructions if the other
// instructions meet some requirements we deem safe:
+ // - They are not pseudo instructions.
// - They are debug instructions. Otherwise,
// - They do not have side-effects, do not access memory and their inputs do
// not depend on the results of the select pseudo-instructions.
@@ -11234,7 +11235,8 @@
continue;
}
if (SequenceMBBI->hasUnmodeledSideEffects() ||
- SequenceMBBI->mayLoadOrStore())
+ SequenceMBBI->mayLoadOrStore() ||
+ SequenceMBBI->usesCustomInsertionHook())
break;
if (llvm::any_of(SequenceMBBI->operands(), [&](MachineOperand &MO) {
return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg());
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