[PATCH] D137653: [TableGen] More named sub-operands work.

[Gaëtan Bossu via Phabricator via llvm-commits]

gbossu added inline comments.


================
Comment at: llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp:6557
+  // the decoder doesn't actually call it yet. That will be addressed in a
+  // future change.)
+  return MCDisassembler::Success;
----------------
@jyknight I actually had a local patch which I planned to upstream in the next days, but that was made before your changes. That patch introduces an additional `bit DecodeZeroBitOperand = false;` flag in `DAGOperand` to allow targets to still get decoding callbacks for operands, even if they are encoded with zero bits. It came with a few changes for targets which have these "zero-bit" operands, like AVR, AArch64 or RiscV if I remember correctly.

It kept the default behavior of ignoring "zero-bit" operands when `DecodeZeroBitOperand` is false though. IIRC AMDGPU relies on this mechanism to purposely skip operands. Should I push this patch forward, or will this be superseded by some of your upcoming work by essentially always generating disassembler callbacks?


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  https://reviews.llvm.org/D137653/new/

https://reviews.llvm.org/D137653