[PATCH] D141311: [RISCV] Avoid emitting hardware fences for singlethread fences

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM - two minor nits inline.



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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3677
+
+  // singlethread fences only synchronize with signal handles on the same
+  // thread and thus only need to preserve instruction order, not actually
----------------
handles => handlers


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:3687
+
+
 SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
----------------
Accidental extra whitespace?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141311/new/

https://reviews.llvm.org/D141311