[llvm] 88b3127 - [AArch64] lower abs intrinsic to new ABS instruction in GIsel
Ties Stuij via llvm-commits
llvm-commits at lists.llvm.org
Tue Jan 10 03:46:37 PST 2023
Author: Ties Stuij
Date: 2023-01-10T11:46:28Z
New Revision: 88b3127ed1faade1d51770e65e554d1273ed1039
URL: https://github.com/llvm/llvm-project/commit/88b3127ed1faade1d51770e65e554d1273ed1039
DIFF: https://github.com/llvm/llvm-project/commit/88b3127ed1faade1d51770e65e554d1273ed1039.diff
LOG: [AArch64] lower abs intrinsic to new ABS instruction in GIsel
When feature CSSC is available, the abs intrinsic should map to the
new scalar ABS instruction when using GlobalIsel
spec:
https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/ABS--Absolute-value-
Reviewed By: aemerson
Differential Revision: https://reviews.llvm.org/D139419
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-abs.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index b64df6ae3369d..5bf277163c102 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -749,10 +749,14 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.libcall();
}
- // FIXME: Legal types are only legal with NEON.
- getActionDefinitionsBuilder(G_ABS)
- .lowerIf(isScalar(0))
- .legalFor(PackedVectorAllTypeList);
+ // FIXME: Legal vector types are only legal with NEON.
+ auto &ABSActions = getActionDefinitionsBuilder(G_ABS);
+ if (HasCSSC)
+ ABSActions
+ .legalFor({s32, s64});
+ ABSActions
+ .legalFor(PackedVectorAllTypeList)
+ .lowerIf(isScalar(0));
getActionDefinitionsBuilder(G_VECREDUCE_FADD)
// We only have FADDP to do reduction-like operations. Lower the rest.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-abs.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-abs.mir
index f604a55032144..3123e304116fe 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-abs.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-abs.mir
@@ -1,5 +1,6 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
+# RUN: llc -mtriple=aarch64 -run-pass=legalizer -mattr=+cssc -global-isel-abort=1 %s -o - | FileCheck %s --check-prefix=CHECK-CSSC
---
name: abs_s32
liveins:
@@ -7,11 +8,15 @@ body: |
bb.0:
; CHECK-LABEL: name: abs_s32
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
- ; CHECK: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
- ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]
- ; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
- ; CHECK: $w0 = COPY [[XOR]](s32)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 31
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ASHR]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[ADD]], [[ASHR]]
+ ; CHECK-NEXT: $w0 = COPY [[XOR]](s32)
+ ; CHECK-CSSC-LABEL: name: abs_s32
+ ; CHECK-CSSC: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK-CSSC-NEXT: [[ABS:%[0-9]+]]:_(s32) = G_ABS [[COPY]]
+ ; CHECK-CSSC-NEXT: $w0 = COPY [[ABS]](s32)
%0:_(s32) = COPY $w0
%1:_(s32) = G_ABS %0(s32)
$w0 = COPY %1(s32)
@@ -23,11 +28,15 @@ body: |
bb.0:
; CHECK-LABEL: name: abs_s64
; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
- ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
- ; CHECK: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
- ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ASHR]]
- ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
- ; CHECK: $x0 = COPY [[XOR]](s64)
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 63
+ ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s64) = G_ASHR [[COPY]], [[C]](s64)
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ASHR]]
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[ADD]], [[ASHR]]
+ ; CHECK-NEXT: $x0 = COPY [[XOR]](s64)
+ ; CHECK-CSSC-LABEL: name: abs_s64
+ ; CHECK-CSSC: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK-CSSC-NEXT: [[ABS:%[0-9]+]]:_(s64) = G_ABS [[COPY]]
+ ; CHECK-CSSC-NEXT: $x0 = COPY [[ABS]](s64)
%0:_(s64) = COPY $x0
%1:_(s64) = G_ABS %0(s64)
$x0 = COPY %1(s64)
@@ -41,10 +50,18 @@ body: |
; CHECK-LABEL: name: abs_v4s16
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK: [[ABS:%[0-9]+]]:_(<4 x s16>) = G_ABS [[COPY]]
- ; CHECK: $d0 = COPY [[ABS]](<4 x s16>)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(<4 x s16>) = G_ABS [[COPY]]
+ ; CHECK-NEXT: $d0 = COPY [[ABS]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ ; CHECK-CSSC-LABEL: name: abs_v4s16
+ ; CHECK-CSSC: liveins: $d0
+ ; CHECK-CSSC-NEXT: {{ $}}
+ ; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-CSSC-NEXT: [[ABS:%[0-9]+]]:_(<4 x s16>) = G_ABS [[COPY]]
+ ; CHECK-CSSC-NEXT: $d0 = COPY [[ABS]](<4 x s16>)
+ ; CHECK-CSSC-NEXT: RET_ReallyLR implicit $d0
%0:_(<4 x s16>) = COPY $d0
%1:_(<4 x s16>) = G_ABS %0
$d0 = COPY %1(<4 x s16>)
@@ -60,10 +77,18 @@ body: |
; CHECK-LABEL: name: abs_v8s16
; CHECK: liveins: $q0
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK: [[ABS:%[0-9]+]]:_(<8 x s16>) = G_ABS [[COPY]]
- ; CHECK: $q0 = COPY [[ABS]](<8 x s16>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(<8 x s16>) = G_ABS [[COPY]]
+ ; CHECK-NEXT: $q0 = COPY [[ABS]](<8 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ ; CHECK-CSSC-LABEL: name: abs_v8s16
+ ; CHECK-CSSC: liveins: $q0
+ ; CHECK-CSSC-NEXT: {{ $}}
+ ; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK-CSSC-NEXT: [[ABS:%[0-9]+]]:_(<8 x s16>) = G_ABS [[COPY]]
+ ; CHECK-CSSC-NEXT: $q0 = COPY [[ABS]](<8 x s16>)
+ ; CHECK-CSSC-NEXT: RET_ReallyLR implicit $q0
%0:_(<8 x s16>) = COPY $q0
%1:_(<8 x s16>) = G_ABS %0
$q0 = COPY %1(<8 x s16>)
@@ -79,10 +104,18 @@ body: |
; CHECK-LABEL: name: abs_v2s32
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK: [[ABS:%[0-9]+]]:_(<2 x s32>) = G_ABS [[COPY]]
- ; CHECK: $d0 = COPY [[ABS]](<2 x s32>)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(<2 x s32>) = G_ABS [[COPY]]
+ ; CHECK-NEXT: $d0 = COPY [[ABS]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ ; CHECK-CSSC-LABEL: name: abs_v2s32
+ ; CHECK-CSSC: liveins: $d0
+ ; CHECK-CSSC-NEXT: {{ $}}
+ ; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-CSSC-NEXT: [[ABS:%[0-9]+]]:_(<2 x s32>) = G_ABS [[COPY]]
+ ; CHECK-CSSC-NEXT: $d0 = COPY [[ABS]](<2 x s32>)
+ ; CHECK-CSSC-NEXT: RET_ReallyLR implicit $d0
%0:_(<2 x s32>) = COPY $d0
%1:_(<2 x s32>) = G_ABS %0
$d0 = COPY %1(<2 x s32>)
@@ -98,10 +131,18 @@ body: |
; CHECK-LABEL: name: abs_v4s32
; CHECK: liveins: $q0
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK: [[ABS:%[0-9]+]]:_(<4 x s32>) = G_ABS [[COPY]]
- ; CHECK: $q0 = COPY [[ABS]](<4 x s32>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(<4 x s32>) = G_ABS [[COPY]]
+ ; CHECK-NEXT: $q0 = COPY [[ABS]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ ; CHECK-CSSC-LABEL: name: abs_v4s32
+ ; CHECK-CSSC: liveins: $q0
+ ; CHECK-CSSC-NEXT: {{ $}}
+ ; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK-CSSC-NEXT: [[ABS:%[0-9]+]]:_(<4 x s32>) = G_ABS [[COPY]]
+ ; CHECK-CSSC-NEXT: $q0 = COPY [[ABS]](<4 x s32>)
+ ; CHECK-CSSC-NEXT: RET_ReallyLR implicit $q0
%0:_(<4 x s32>) = COPY $q0
%1:_(<4 x s32>) = G_ABS %0
$q0 = COPY %1(<4 x s32>)
@@ -117,10 +158,18 @@ body: |
; CHECK-LABEL: name: abs_v4s8
; CHECK: liveins: $d0
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK: [[ABS:%[0-9]+]]:_(<8 x s8>) = G_ABS [[COPY]]
- ; CHECK: $d0 = COPY [[ABS]](<8 x s8>)
- ; CHECK: RET_ReallyLR implicit $d0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(<8 x s8>) = G_ABS [[COPY]]
+ ; CHECK-NEXT: $d0 = COPY [[ABS]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $d0
+ ; CHECK-CSSC-LABEL: name: abs_v4s8
+ ; CHECK-CSSC: liveins: $d0
+ ; CHECK-CSSC-NEXT: {{ $}}
+ ; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-CSSC-NEXT: [[ABS:%[0-9]+]]:_(<8 x s8>) = G_ABS [[COPY]]
+ ; CHECK-CSSC-NEXT: $d0 = COPY [[ABS]](<8 x s8>)
+ ; CHECK-CSSC-NEXT: RET_ReallyLR implicit $d0
%0:_(<8 x s8>) = COPY $d0
%1:_(<8 x s8>) = G_ABS %0
$d0 = COPY %1(<8 x s8>)
@@ -136,10 +185,18 @@ body: |
; CHECK-LABEL: name: abs_v16s8
; CHECK: liveins: $q0
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK: [[ABS:%[0-9]+]]:_(<16 x s8>) = G_ABS [[COPY]]
- ; CHECK: $q0 = COPY [[ABS]](<16 x s8>)
- ; CHECK: RET_ReallyLR implicit $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[ABS:%[0-9]+]]:_(<16 x s8>) = G_ABS [[COPY]]
+ ; CHECK-NEXT: $q0 = COPY [[ABS]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR implicit $q0
+ ; CHECK-CSSC-LABEL: name: abs_v16s8
+ ; CHECK-CSSC: liveins: $q0
+ ; CHECK-CSSC-NEXT: {{ $}}
+ ; CHECK-CSSC-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-CSSC-NEXT: [[ABS:%[0-9]+]]:_(<16 x s8>) = G_ABS [[COPY]]
+ ; CHECK-CSSC-NEXT: $q0 = COPY [[ABS]](<16 x s8>)
+ ; CHECK-CSSC-NEXT: RET_ReallyLR implicit $q0
%0:_(<16 x s8>) = COPY $q0
%1:_(<16 x s8>) = G_ABS %0
$q0 = COPY %1(<16 x s8>)
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