[llvm] e3becfa - [DirectX backend] Remove unused bitcode block for dxil
Xiang Li via llvm-commits
llvm-commits at lists.llvm.org
Mon Jan 9 16:07:01 PST 2023
Author: Xiang Li
Date: 2023-01-09T19:06:33-05:00
New Revision: e3becfacfd6f606671e0d338ac57e06f9cecb2e3
URL: https://github.com/llvm/llvm-project/commit/e3becfacfd6f606671e0d338ac57e06f9cecb2e3
DIFF: https://github.com/llvm/llvm-project/commit/e3becfacfd6f606671e0d338ac57e06f9cecb2e3.diff
LOG: [DirectX backend] Remove unused bitcode block for dxil
DXIL doesn't need uselist strtab and symtab blocks which are not supported by llvm3.7 bitcode.
Differential Revision: https://reviews.llvm.org/D141328
Added:
Modified:
llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.h
llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
llvm/test/tools/dxil-dis/BasicIR.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
index dcb8ebaa38c69..0aafb08091f38 100644
--- a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
+++ b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
@@ -344,8 +344,6 @@ class DXILBitcodeWriter {
void writeFunctionLevelValueSymbolTable(const ValueSymbolTable &VST);
void writeGlobalValueSymbolTable(
DenseMap<const Function *, uint64_t> &FunctionToBitcodeIndex);
- void writeUseList(UseListOrder &&Order);
- void writeUseListBlock(const Function *F);
void writeFunction(const Function &F);
void writeBlockInfo();
@@ -383,7 +381,7 @@ dxil::BitcodeWriter::BitcodeWriter(SmallVectorImpl<char> &Buffer,
Stream->Emit(0xD, 4);
}
-dxil::BitcodeWriter::~BitcodeWriter() { assert(WroteStrtab); }
+dxil::BitcodeWriter::~BitcodeWriter() { }
/// Write the specified module to the specified output stream.
void dxil::WriteDXILToFile(const Module &M, raw_ostream &Out) {
@@ -398,8 +396,6 @@ void dxil::WriteDXILToFile(const Module &M, raw_ostream &Out) {
BitcodeWriter Writer(Buffer, dyn_cast<raw_fd_stream>(&Out));
Writer.writeModule(M);
- Writer.writeSymtab();
- Writer.writeStrtab();
// Write the generated bitstream to "Out".
if (!Buffer.empty())
@@ -419,53 +415,7 @@ void BitcodeWriter::writeBlob(unsigned Block, unsigned Record, StringRef Blob) {
Stream->ExitBlock();
}
-void BitcodeWriter::writeSymtab() {
- assert(!WroteStrtab && !WroteSymtab);
-
- // If any module has module-level inline asm, we will require a registered asm
- // parser for the target so that we can create an accurate symbol table for
- // the module.
- for (Module *M : Mods) {
- if (M->getModuleInlineAsm().empty())
- continue;
- }
-
- WroteSymtab = true;
- SmallVector<char, 0> Symtab;
- // The irsymtab::build function may be unable to create a symbol table if the
- // module is malformed (e.g. it contains an invalid alias). Writing a symbol
- // table is not required for correctness, but we still want to be able to
- // write malformed modules to bitcode files, so swallow the error.
- if (Error E = irsymtab::build(Mods, Symtab, StrtabBuilder, Alloc)) {
- consumeError(std::move(E));
- return;
- }
-
- writeBlob(bitc::SYMTAB_BLOCK_ID, bitc::SYMTAB_BLOB,
- {Symtab.data(), Symtab.size()});
-}
-
-void BitcodeWriter::writeStrtab() {
- assert(!WroteStrtab);
-
- std::vector<char> Strtab;
- StrtabBuilder.finalizeInOrder();
- Strtab.resize(StrtabBuilder.getSize());
- StrtabBuilder.write((uint8_t *)Strtab.data());
-
- writeBlob(bitc::STRTAB_BLOCK_ID, bitc::STRTAB_BLOB,
- {Strtab.data(), Strtab.size()});
-
- WroteStrtab = true;
-}
-
-void BitcodeWriter::copyStrtab(StringRef Strtab) {
- writeBlob(bitc::STRTAB_BLOCK_ID, bitc::STRTAB_BLOB, Strtab);
- WroteStrtab = true;
-}
-
void BitcodeWriter::writeModule(const Module &M) {
- assert(!WroteStrtab);
// The Mods vector is used by irsymtab::build, which requires non-const
// Modules in case it needs to materialize metadata. But the bitcode writer
@@ -2673,35 +2623,6 @@ void DXILBitcodeWriter::writeFunctionLevelValueSymbolTable(
Stream.ExitBlock();
}
-void DXILBitcodeWriter::writeUseList(UseListOrder &&Order) {
- assert(Order.Shuffle.size() >= 2 && "Shuffle too small");
- unsigned Code;
- if (isa<BasicBlock>(Order.V))
- Code = bitc::USELIST_CODE_BB;
- else
- Code = bitc::USELIST_CODE_DEFAULT;
-
- SmallVector<uint64_t, 64> Record(Order.Shuffle.begin(), Order.Shuffle.end());
- Record.push_back(VE.getValueID(Order.V));
- Stream.EmitRecord(Code, Record);
-}
-
-void DXILBitcodeWriter::writeUseListBlock(const Function *F) {
- auto hasMore = [&]() {
- return !VE.UseListOrders.empty() && VE.UseListOrders.back().F == F;
- };
- if (!hasMore())
- // Nothing to do.
- return;
-
- Stream.EnterSubblock(bitc::USELIST_BLOCK_ID, 3);
- while (hasMore()) {
- writeUseList(std::move(VE.UseListOrders.back()));
- VE.UseListOrders.pop_back();
- }
- Stream.ExitBlock();
-}
-
/// Emit a function body to the module stream.
void DXILBitcodeWriter::writeFunction(const Function &F) {
Stream.EnterSubblock(bitc::FUNCTION_BLOCK_ID, 4);
@@ -2770,7 +2691,6 @@ void DXILBitcodeWriter::writeFunction(const Function &F) {
if (NeedsMetadataAttachment)
writeFunctionMetadataAttachment(F);
- writeUseListBlock(&F);
VE.purgeFunction();
Stream.ExitBlock();
}
@@ -2997,9 +2917,6 @@ void DXILBitcodeWriter::write() {
// function level table.
writeFunctionLevelValueSymbolTable(M.getValueSymbolTable());
- // Emit module-level use-lists.
- writeUseListBlock(nullptr);
-
// Emit function bodies.
for (const Function &F : M)
if (!F.isDeclaration())
diff --git a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.h b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.h
index 289f692f0f822..9e26cd6d9738c 100644
--- a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.h
+++ b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.h
@@ -38,8 +38,6 @@ class BitcodeWriter {
// string table.
BumpPtrAllocator Alloc;
- bool WroteStrtab = false, WroteSymtab = false;
-
void writeBlob(unsigned Block, unsigned Record, StringRef Blob);
std::vector<Module *> Mods;
@@ -50,23 +48,6 @@ class BitcodeWriter {
~BitcodeWriter();
- /// Attempt to write a symbol table to the bitcode file. This must be called
- /// at most once after all modules have been written.
- ///
- /// A reader does not require a symbol table to interpret a bitcode file;
- /// the symbol table is needed only to improve link-time performance. So
- /// this function may decide not to write a symbol table. It may so decide
- /// if, for example, the target is unregistered or the IR is malformed.
- void writeSymtab();
-
- /// Write the bitcode file's string table. This must be called exactly once
- /// after all modules and the optional symbol table have been written.
- void writeStrtab();
-
- /// Copy the string table for another module into this bitcode file. This
- /// should be called after copying the module itself into the bitcode file.
- void copyStrtab(StringRef Strtab);
-
/// Write the specified module to the buffer specified at construction time.
void writeModule(const Module &M);
};
diff --git a/llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp b/llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
index 1e32141cc098c..b0a71003bcf32 100644
--- a/llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
+++ b/llvm/lib/Target/DirectX/DXILWriter/DXILWriterPass.cpp
@@ -93,10 +93,10 @@ class EmbedDXILPass : public llvm::ModulePass {
} // namespace
char WriteDXILPass::ID = 0;
-INITIALIZE_PASS_BEGIN(WriteDXILPass, "write-bitcode", "Write Bitcode", false,
- true)
+INITIALIZE_PASS_BEGIN(WriteDXILPass, "dxil-write-bitcode", "Write Bitcode",
+ false, true)
INITIALIZE_PASS_DEPENDENCY(ModuleSummaryIndexWrapperPass)
-INITIALIZE_PASS_END(WriteDXILPass, "write-bitcode", "Write Bitcode", false,
+INITIALIZE_PASS_END(WriteDXILPass, "dxil-write-bitcode", "Write Bitcode", false,
true)
ModulePass *llvm::createDXILWriterPass(raw_ostream &Str) {
diff --git a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
index c72af04fa31d2..59e6fcb44d5ae 100644
--- a/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
+++ b/llvm/lib/Target/DirectX/DirectXTargetMachine.cpp
@@ -41,6 +41,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeDirectXTarget() {
auto *PR = PassRegistry::getPassRegistry();
initializeDXILPrepareModulePass(*PR);
initializeEmbedDXILPassPass(*PR);
+ initializeWriteDXILPassPass(*PR);
initializeDXILOpLoweringLegacyPass(*PR);
initializeDXILTranslateMetadataPass(*PR);
initializeDXILResourceWrapperPass(*PR);
diff --git a/llvm/test/tools/dxil-dis/BasicIR.ll b/llvm/test/tools/dxil-dis/BasicIR.ll
index a08537d16abb5..8f961f095754d 100644
--- a/llvm/test/tools/dxil-dis/BasicIR.ll
+++ b/llvm/test/tools/dxil-dis/BasicIR.ll
@@ -1,11 +1,20 @@
; RUN: llc --filetype=obj %s -o - | dxil-dis -o - | FileCheck %s
+; RUN: llc --filetype=obj %s --stop-after=dxil-write-bitcode -o %t | llvm-bcanalyzer --dump-blockinfo %t | FileCheck %s --check-prefix=BLOCK_INFO
+
; CHECK: define i32 @foo(i32 %X, i32 %Y) {
; CHECK: %Z = sub i32 %X, %Y
; CHECK: %Q = add i32 %Z, %Y
; CHECK: ret i32 %Q
; CHECK: }
+; BLOCK_INFO:Stream type: LLVM IR
+; Make sure uselist strtab and symtab is not in dxil.
+; BLOCK_INFO-NOT:USELIST_BLOCK_ID
+; BLOCK_INFO-NOT:STRTAB_BLOCK
+; BLOCK_INFO-NOT:SYMTAB_BLOCK
+
+
target triple = "dxil-unknown-shadermodel6.7-library"
define i32 @foo(i32 %X, i32 %Y) {
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