[PATCH] D140993: [DAGCombine] fold (sext (sext_inreg x)) -> (sext (trunc x))

[Amaury SECHET via Phabricator via llvm-commits]

deadalnix updated this revision to Diff 487567.
deadalnix added a comment.
Herald added a subscriber: pengfei.

Specialize the transform, which avoids problems with the transform creating an infinite loop.

Make sure we materialize improvements in sdiv_fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140993/new/

https://reviews.llvm.org/D140993

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/test/CodeGen/X86/sdiv_fix.ll
  llvm/test/CodeGen/X86/sdiv_fix_sat.ll


Index: llvm/test/CodeGen/X86/sdiv_fix_sat.ll
===================================================================
--- llvm/test/CodeGen/X86/sdiv_fix_sat.ll
+++ llvm/test/CodeGen/X86/sdiv_fix_sat.ll
@@ -81,10 +81,8 @@
 ;
 ; X64-LABEL: func2:
 ; X64:       # %bb.0:
-; X64-NEXT:    movsbl %dil, %eax
-; X64-NEXT:    movsbl %sil, %ecx
-; X64-NEXT:    movswl %cx, %esi
-; X64-NEXT:    movswl %ax, %ecx
+; X64-NEXT:    movsbl %sil, %esi
+; X64-NEXT:    movsbl %dil, %ecx
 ; X64-NEXT:    shll $14, %ecx
 ; X64-NEXT:    movl %ecx, %eax
 ; X64-NEXT:    cltd
Index: llvm/test/CodeGen/X86/sdiv_fix.ll
===================================================================
--- llvm/test/CodeGen/X86/sdiv_fix.ll
+++ llvm/test/CodeGen/X86/sdiv_fix.ll
@@ -65,10 +65,8 @@
 define i16 @func2(i8 %x, i8 %y) nounwind {
 ; X64-LABEL: func2:
 ; X64:       # %bb.0:
-; X64-NEXT:    movsbl %dil, %eax
-; X64-NEXT:    movsbl %sil, %ecx
-; X64-NEXT:    movswl %cx, %esi
-; X64-NEXT:    movswl %ax, %ecx
+; X64-NEXT:    movsbl %sil, %esi
+; X64-NEXT:    movsbl %dil, %ecx
 ; X64-NEXT:    shll $14, %ecx
 ; X64-NEXT:    movl %ecx, %eax
 ; X64-NEXT:    cltd
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -12357,6 +12357,16 @@
   if (N0.getOpcode() == ISD::SIGN_EXTEND || N0.getOpcode() == ISD::ANY_EXTEND)
     return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, N0.getOperand(0));
 
+  // fold (sext (sext_inreg x)) -> (sext (trunc x))
+  if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG) {
+    SDValue N00 = N0.getOperand(0);
+    EVT ExtVT = cast<VTSDNode>(N0->getOperand(1))->getVT();
+    if (N00.getOpcode() == ISD::TRUNCATE && (!LegalOperations || TLI.isTypeLegal(ExtVT))) {
+      SDValue T = DAG.getNode(ISD::TRUNCATE, DL, ExtVT, N00.getOperand(0));
+      return DAG.getNode(ISD::SIGN_EXTEND, DL, VT, T);
+    }
+  }
+
   if (N0.getOpcode() == ISD::TRUNCATE) {
     // fold (sext (truncate (load x))) -> (sext (smaller load x))
     // fold (sext (truncate (srl (load x), c))) -> (sext (smaller load (x+c/n)))


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