[PATCH] D141311: [RISCV] Avoid emitting hardware fences for singlethread fences

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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singlethread fences only synchronize with code running on the same hardware thread (i.e. signal handlers).  Because of this, we need to prevent instruction rewordering, but do not need to emit hardware fence instructions.

The implementation strategy here matches many other backends.  The main motivation of this patch is to introduce the MEMBARRIER node and get some test coverage for it.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141311

Files:
  llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/atomic-fence.ll

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