[llvm] 7ca0af8 - [RISCV] Consolidate test lines in fence lowering test

[Philip Reames via llvm-commits]

Author: Philip Reames
Date: 2023-01-09T11:00:47-08:00
New Revision: 7ca0af89431a62c07effd96eced74c4db88b47bc

URL: https://github.com/llvm/llvm-project/commit/7ca0af89431a62c07effd96eced74c4db88b47bc
DIFF: https://github.com/llvm/llvm-project/commit/7ca0af89431a62c07effd96eced74c4db88b47bc.diff

LOG: [RISCV] Consolidate test lines in fence lowering test

These are identical for RV32 and RV64.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/atomic-fence.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/RISCV/atomic-fence.ll b/llvm/test/CodeGen/RISCV/atomic-fence.ll
index f69e9b37e84e..1697e05603a0 100644
--- a/llvm/test/CodeGen/RISCV/atomic-fence.ll
+++ b/llvm/test/CodeGen/RISCV/atomic-fence.ll
@@ -1,121 +1,81 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN:   | FileCheck %s
 ; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV32I %s
+; RUN:   | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN:   | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
-; RUN:   | FileCheck -check-prefix=RV64I %s
+; RUN:   | FileCheck %s
 
 define void @fence_acquire() nounwind {
-; RV32I-LABEL: fence_acquire:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    fence r, rw
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: fence_acquire:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    fence r, rw
-; RV64I-NEXT:    ret
+; CHECK-LABEL: fence_acquire:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fence r, rw
+; CHECK-NEXT:    ret
   fence acquire
   ret void
 }
 
 define void @fence_release() nounwind {
-; RV32I-LABEL: fence_release:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    fence rw, w
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: fence_release:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    fence rw, w
-; RV64I-NEXT:    ret
+; CHECK-LABEL: fence_release:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fence rw, w
+; CHECK-NEXT:    ret
   fence release
   ret void
 }
 
 define void @fence_acq_rel() nounwind {
-; RV32I-LABEL: fence_acq_rel:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    fence.tso
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: fence_acq_rel:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    fence.tso
-; RV64I-NEXT:    ret
+; CHECK-LABEL: fence_acq_rel:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fence.tso
+; CHECK-NEXT:    ret
   fence acq_rel
   ret void
 }
 
 define void @fence_seq_cst() nounwind {
-; RV32I-LABEL: fence_seq_cst:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    fence rw, rw
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: fence_seq_cst:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    fence rw, rw
-; RV64I-NEXT:    ret
+; CHECK-LABEL: fence_seq_cst:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fence rw, rw
+; CHECK-NEXT:    ret
   fence seq_cst
   ret void
 }
 
 define void @fence_singlethread_acquire() nounwind {
-; RV32I-LABEL: fence_singlethread_acquire:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    fence r, rw
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: fence_singlethread_acquire:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    fence r, rw
-; RV64I-NEXT:    ret
+; CHECK-LABEL: fence_singlethread_acquire:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fence r, rw
+; CHECK-NEXT:    ret
   fence syncscope("singlethread") acquire
   ret void
 }
 
 define void @fence_singlethread_release() nounwind {
-; RV32I-LABEL: fence_singlethread_release:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    fence rw, w
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: fence_singlethread_release:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    fence rw, w
-; RV64I-NEXT:    ret
+; CHECK-LABEL: fence_singlethread_release:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fence rw, w
+; CHECK-NEXT:    ret
   fence syncscope("singlethread") release
   ret void
 }
 
 define void @fence_singlethread_acq_rel() nounwind {
-; RV32I-LABEL: fence_singlethread_acq_rel:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    fence.tso
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: fence_singlethread_acq_rel:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    fence.tso
-; RV64I-NEXT:    ret
+; CHECK-LABEL: fence_singlethread_acq_rel:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fence.tso
+; CHECK-NEXT:    ret
   fence syncscope("singlethread") acq_rel
   ret void
 }
 
 define void @fence_singlethread_seq_cst() nounwind {
-; RV32I-LABEL: fence_singlethread_seq_cst:
-; RV32I:       # %bb.0:
-; RV32I-NEXT:    fence rw, rw
-; RV32I-NEXT:    ret
-;
-; RV64I-LABEL: fence_singlethread_seq_cst:
-; RV64I:       # %bb.0:
-; RV64I-NEXT:    fence rw, rw
-; RV64I-NEXT:    ret
+; CHECK-LABEL: fence_singlethread_seq_cst:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fence rw, rw
+; CHECK-NEXT:    ret
   fence syncscope("singlethread") seq_cst
   ret void
 }