[PATCH] D117502: [LV] Combine vector reductions parts in tree instead of serially.

Mon Jan 9 09:43:48 PST 2023

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In D117502#3254056 <https://reviews.llvm.org/D117502#3254056>, @dmgreen wrote:

>> It won't have a massive impact in general, but it shaves off a few cycles, depending on the interleave count.
>>
>> AFAICT the redistributions done in the https://godbolt.org/z/z4nf5hPna are done by `ReassoicatePass`, which likes to turn parallel reduction trees into serial ones (? but that's a separate issue I think), like for `@float2`, which looks like it got serialized. I don't think any passes that run after the vectorizer try to improve the length of reduction chains: https://godbolt.org/z/v4K4aK3a1
>
> Do we think this is something that should be done in general? This looks like it will allow the reordering of fp instructions under `-hints-allow-reordering=true` without fast flags, which would not otherwise be reassociatable. But the other cases could always be done by the backend if it considered it profitable.

It looks like there was a restriction in the MachineCombiner's reassociate logic that was prevent reassociation here. I think the restriction can be removed, then those cases should be handled properly in the backend: D141302 <https://reviews.llvm.org/D141302>

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