[PATCH] D139813: [PowerPC] Improve materialization for immediates which is almost a 32 bit splat.

[ChenZheng via Phabricator via llvm-commits]

shchenz added a comment.

In D139813#4034807 <https://reviews.llvm.org/D139813#4034807>, @Esme wrote:

> Addressed comments and verified the materialization results.
> However, I can't find a proper instruction to turn `0xABCD ADDD ABCD ADDD` into `0xABCD ABCD ABCD ADDD`, ie. modify `Lo16OfHi32 (bits 32...47)`, so I didn't handle the pattern like `0xABCD ABCD ABCD ADDD`.

Thanks, the new selection seems correct. For pattern `0xABCD ABCD ABCD ADDD`, yeah, I can not find a 4 instruction selection for it either.



================
Comment at: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:1334
+  // splat of a 32 bit immediate.
+  if (InstCntDirect > 4) {
+    uint32_t Hi16OfHi32 = (Hi_32(Imm) >> 16) & 0xffff;
----------------
Esme wrote:
> shchenz wrote:
> > For compile time concern, since the 1 instruction patterns for `Imm & 0xffffffff00000000` are simple, can we move the new code before line 1318 and do some simple check for 1 instruction pattern in `selectI64ImmDirect`? 
> Sorry I didn't quite understand this comment.
> `Imm & 0xffffffff00000000` always takes more than 1 instruction because it is impossible to match the 1-instruction-pattern:
> ```
>   // 1-1) Patterns : {zeros}{15-bit valve}
>   //                 {ones}{15-bit valve}
> 
>   // 1-2) Patterns : {zeros}{15-bit valve}{16 zeros}
>   //                 {ones}{15-bit valve}{16 zeros}
> ```
I mean the new codes can be moved before line 1317 with some simple checks. For example if select `Imm & 0xffffffff00000000` requires no less than 2 instructions and the lower 32 bit also requires 2 instructions, the new splat handling can be done first. Generating a 5 instruction pattern and then marking them as dead can be avoided even the new codes are hit.


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https://reviews.llvm.org/D139813