[PATCH] D141247: [GlobalISelEmitter][WIP] handle operand without MVT/class

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
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There are some patterns in td files without MVT/class set for some operands in target
pattern that are from the source pattern. This prevents GlobalISelEmitter from adding 
them as a valid rule, because the target child operand is an unsupported kind operand.
For now, for a leaf child, only `IntInit` and `DefInit` are handled in GlobalISelEmitter.

This issue can be workaround by adding MVT/class to the patterns in the td files, like
the workarounds for patterns anyext and setcc in PPCInstrInfo.td in D140878 <https://reviews.llvm.org/D140878>.

To avoid adding the same workarounds for other patterns in td files, this patch tries to
handle the `UnsetInit` case in GlobalISelEmitter.

Adding the new handling allows us to remove the workarounds in the td files and also
generates many selection rules for PPC target.

This is a WIP patch and there are about 90 cases left unfixed, most of them are for `AMDGPU/GlobalISel/`.

I am not familiar with the AMDGPU arch, so I post this initial draft patch for comments 
first to check this is a right fix and the cases change make senses.

There are also some AMDGPU cases fail because of machine verify error.

  # After InstructionSelect
  # Machine code for function v_mul_i16_signext: IsSSA, TracksLiveness, Legalized, RegBankSelected, Selected
  
  bb.1 (%ir-block.0):
    liveins: $vgpr0, $vgpr1
    %2:vgpr_32 = COPY $vgpr0
    %4:vgpr_32 = COPY $vgpr1
    %6:vgpr_32 = V_MUL_LO_U16_e64 %2:vgpr_32, %4:vgpr_32, implicit $exec
    %9:sreg_32 = S_MOV_B32 16
    %8:sreg_32 = S_MOV_B32 0
    %7:vgpr_32 = V_BFE_I32_e64 %6:vgpr_32, %8:sreg_32, %9:sreg_32, implicit $exec
    $vgpr0 = COPY %7:vgpr_32
    SI_RETURN implicit $vgpr0
  
  # End machine code for function v_mul_i16_signext.
  
  *** Bad machine code: VOP* instruction violates constant bus restriction ***
  - function:    v_mul_i16_signext
  - basic block: %bb.1  (0x1003fec2298)
  - instruction: %7:vgpr_32 = V_BFE_I32_e64 %6:vgpr_32, %8:sreg_32, %9:sreg_32, implicit $exec

Not sure this is expected.

Thanks in advance for your comments.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D141247

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshl.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.a16.dim.ll
  llvm/utils/TableGen/GlobalISelEmitter.cpp

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