[llvm] e10e936 - [DebugInfo][NFC] Add new MachineOperand type and change DBG_INSTR_REF syntax
Stephen Tozer via llvm-commits
llvm-commits at lists.llvm.org
Fri Jan 6 10:04:00 PST 2023
Author: Stephen Tozer
Date: 2023-01-06T18:03:48Z
New Revision: e10e936315410abd222eb58911b1e20fbfa80baf
URL: https://github.com/llvm/llvm-project/commit/e10e936315410abd222eb58911b1e20fbfa80baf
DIFF: https://github.com/llvm/llvm-project/commit/e10e936315410abd222eb58911b1e20fbfa80baf.diff
LOG: [DebugInfo][NFC] Add new MachineOperand type and change DBG_INSTR_REF syntax
This patch makes two notable changes to the MIR debug info representation,
which result in different MIR output but identical final DWARF output (NFC
w.r.t. the full compilation). The two changes are:
* The introduction of a new MachineOperand type, MO_DbgInstrRef, which
consists of two unsigned numbers that are used to index an instruction
and an output operand within that instruction, having a meaning
identical to first two operands of the current DBG_INSTR_REF
instruction. This operand is only used in DBG_INSTR_REF (see below).
* A change in syntax for the DBG_INSTR_REF instruction, shuffling the
operands to make it resemble DBG_VALUE_LIST instead of DBG_VALUE,
and replacing the first two operands with a single MO_DbgInstrRef-type
operand.
This patch is the first of a set that will allow DBG_INSTR_REF
instructions to refer to multiple machine locations in the same manner
as DBG_VALUE_LIST.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D129372
Added:
Modified:
llvm/docs/MIRLangRef.rst
llvm/include/llvm/CodeGen/MachineInstr.h
llvm/include/llvm/CodeGen/MachineInstrBuilder.h
llvm/include/llvm/CodeGen/MachineOperand.h
llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
llvm/lib/CodeGen/LiveDebugVariables.cpp
llvm/lib/CodeGen/MIRParser/MILexer.cpp
llvm/lib/CodeGen/MIRParser/MILexer.h
llvm/lib/CodeGen/MIRParser/MIParser.cpp
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
llvm/lib/CodeGen/MachineFunction.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/MachineOperand.cpp
llvm/lib/CodeGen/MachineSink.cpp
llvm/lib/CodeGen/MachineStableHash.cpp
llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
llvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll
llvm/test/DebugInfo/ARM/instr-ref-tcreturn.ll
llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir
llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir
llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir
llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir
llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir
llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll
llvm/test/DebugInfo/X86/dbg-value-funcarg.ll
llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll
llvm/test/DebugInfo/X86/dbg-value-funcarg4.ll
llvm/test/DebugInfo/X86/instr-ref-dbg-declare.ll
llvm/test/DebugInfo/X86/instr-ref-dyn-alloca-win32.ll
llvm/test/DebugInfo/X86/instr-ref-ir-reg-read.ll
llvm/test/DebugInfo/X86/instr-ref-sdag-empty-vreg.ll
llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll
llvm/test/DebugInfo/X86/pr34545.ll
llvm/test/DebugInfo/X86/pr40427.ll
llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll
llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll
llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll
llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
llvm/test/DebugInfo/X86/sdag-ir-salvage.ll
llvm/test/DebugInfo/X86/sdag-salvage-add.ll
llvm/test/DebugInfo/X86/sdag-transfer-dbgvalue.ll
llvm/test/DebugInfo/assignment-tracking/X86/loop-sink.ll
llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll
llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll
llvm/test/DebugInfo/assignment-tracking/X86/sdag-ir-salvage-assign.ll
llvm/test/DebugInfo/assignment-tracking/X86/sdag-transfer-dbgassign.ll
Removed:
################################################################################
diff --git a/llvm/docs/MIRLangRef.rst b/llvm/docs/MIRLangRef.rst
index e7b368d38f2b9..db8b275f502c8 100644
--- a/llvm/docs/MIRLangRef.rst
+++ b/llvm/docs/MIRLangRef.rst
@@ -460,7 +460,7 @@ is preferred.
Machine Operands
----------------
-There are seventeen
diff erent kinds of machine operands, and all of them can be
+There are eighteen
diff erent kinds of machine operands, and all of them can be
serialized.
Immediate Operands
@@ -736,6 +736,19 @@ The syntax is:
EH_LABEL <mcsymbol Ltmp1>
+Debug Instruction Reference Operands
+^^^^^^^^^^^^^^^^^
+
+A debug instruction reference operand is a pair of indices, referring to an
+instruction and an operand within that instruction respectively; see
+:ref:`Instruction referencing locations <instruction-referencing-locations>`.
+
+The example below uses a reference to Instruction 1, Operand 0:
+
+.. code-block:: text
+
+ DBG_INSTR_REF !123, !DIExpression(), dbg-instr-ref(1, 0), debug-location !456
+
CFIIndex Operands
^^^^^^^^^^^^^^^^^
@@ -886,6 +899,8 @@ variable. The second operand (``IsIndirect``) is deprecated and to be deleted.
All additional qualifiers for the variable location should be made through the
expression metadata.
+.. _instruction-referencing-locations:
+
Instruction referencing locations
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -898,16 +913,16 @@ instruction number and operand number. Consider the example below:
.. code-block:: text
$rbp = MOV64ri 0, debug-instr-number 1, debug-location !12
- DBG_INSTR_REF 1, 0, !123, !DIExpression(), debug-location !456
+ DBG_INSTR_REF !123, !DIExpression(), dbg-instr-ref(1, 0), debug-location !456
Instruction numbers are directly attached to machine instructions with an
optional ``debug-instr-number`` attachment, before the optional
``debug-location`` attachment. The value defined in ``$rbp`` in the code
above would be identified by the pair ``<1, 0>``.
-The first two operands of the ``DBG_INSTR_REF`` above record the instruction
+The 3rd operand of the ``DBG_INSTR_REF`` above records the instruction
and operand number ``<1, 0>``, identifying the value defined by the ``MOV64ri``.
-The additional operands to ``DBG_INSTR_REF`` are identical to ``DBG_VALUE``,
+The first two operands to ``DBG_INSTR_REF`` are identical to ``DBG_VALUE_LIST``,
and the ``DBG_INSTR_REF`` s position records where the variable takes on the
designated value in the same way.
diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h
index 21db4667886dd..b062f2c366f70 100644
--- a/llvm/include/llvm/CodeGen/MachineInstr.h
+++ b/llvm/include/llvm/CodeGen/MachineInstr.h
@@ -661,17 +661,17 @@ class MachineInstr
/// Returns a range over all operands that are used to determine the variable
/// location for this DBG_VALUE instruction.
iterator_range<mop_iterator> debug_operands() {
- assert(isDebugValue() && "Must be a debug value instruction.");
- return isDebugValueList()
- ? make_range(operands_begin() + 2, operands_end())
- : make_range(operands_begin(), operands_begin() + 1);
+ assert((isDebugValueLike()) && "Must be a debug value instruction.");
+ return isNonListDebugValue()
+ ? make_range(operands_begin(), operands_begin() + 1)
+ : make_range(operands_begin() + 2, operands_end());
}
/// \copydoc debug_operands()
iterator_range<const_mop_iterator> debug_operands() const {
- assert(isDebugValue() && "Must be a debug value instruction.");
- return isDebugValueList()
- ? make_range(operands_begin() + 2, operands_end())
- : make_range(operands_begin(), operands_begin() + 1);
+ assert((isDebugValueLike()) && "Must be a debug value instruction.");
+ return isNonListDebugValue()
+ ? make_range(operands_begin(), operands_begin() + 1)
+ : make_range(operands_begin() + 2, operands_end());
}
/// Returns a range over all explicit operands that are register definitions.
/// Implicit definition are not included!
@@ -1270,6 +1270,7 @@ class MachineInstr
}
bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; }
bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; }
+ bool isDebugValueLike() const { return isDebugValue() || isDebugRef(); }
bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; }
bool isDebugInstr() const {
return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI();
diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
index 7af53cbb43bb0..04cb331e5d04c 100644
--- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
+++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h
@@ -235,8 +235,8 @@ class MachineInstrBuilder {
const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
MI->addOperand(*MF, MachineOperand::CreateMetadata(MD));
- assert((MI->isDebugValue() ? static_cast<bool>(MI->getDebugVariable())
- : true) &&
+ assert((MI->isDebugValueLike() ? static_cast<bool>(MI->getDebugVariable())
+ : true) &&
"first MDNode argument of a DBG_VALUE not a variable");
assert((MI->isDebugLabel() ? static_cast<bool>(MI->getDebugLabel())
: true) &&
@@ -484,13 +484,6 @@ MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
Register Reg, const MDNode *Variable,
const MDNode *Expr);
-/// This version of the builder builds a DBG_VALUE intrinsic
-/// for a MachineOperand.
-MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
- const MCInstrDesc &MCID, bool IsIndirect,
- const MachineOperand &MO, const MDNode *Variable,
- const MDNode *Expr);
-
/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
/// for a MachineOperand.
MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
@@ -507,16 +500,8 @@ MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
Register Reg, const MDNode *Variable,
const MDNode *Expr);
-/// This version of the builder builds a DBG_VALUE intrinsic
-/// for a machine operand and inserts it at position I.
-MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
- MachineBasicBlock::iterator I, const DebugLoc &DL,
- const MCInstrDesc &MCID, bool IsIndirect,
- MachineOperand &MO, const MDNode *Variable,
- const MDNode *Expr);
-
-/// This version of the builder builds a DBG_VALUE or DBG_VALUE_LIST intrinsic
-/// for a machine operand and inserts it at position I.
+/// This version of the builder builds a DBG_VALUE, DBG_INSTR_REF, or
+/// DBG_VALUE_LIST intrinsic for a machine operand and inserts it at position I.
MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I, const DebugLoc &DL,
const MCInstrDesc &MCID, bool IsIndirect,
diff --git a/llvm/include/llvm/CodeGen/MachineOperand.h b/llvm/include/llvm/CodeGen/MachineOperand.h
index 90f939285f3a2..75710a4542e48 100644
--- a/llvm/include/llvm/CodeGen/MachineOperand.h
+++ b/llvm/include/llvm/CodeGen/MachineOperand.h
@@ -68,7 +68,8 @@ class MachineOperand {
MO_IntrinsicID, ///< Intrinsic ID for ISel
MO_Predicate, ///< Generic predicate for ISel
MO_ShuffleMask, ///< Other IR Constant for ISel (shuffle masks)
- MO_Last = MO_ShuffleMask
+ MO_DbgInstrRef, ///< Integer indices referring to an instruction+operand
+ MO_Last = MO_DbgInstrRef
};
private:
@@ -184,6 +185,11 @@ class MachineOperand {
MachineOperand *Next;
} Reg;
+ struct { // For MO_DbgInstrRef.
+ unsigned InstrIdx;
+ unsigned OpIdx;
+ } InstrRef;
+
/// OffsetedInfo - This struct contains the offset and an object identifier.
/// this represent the object as with an optional offset from it.
struct {
@@ -347,6 +353,7 @@ class MachineOperand {
/// isMetadata - Tests if this is a MO_Metadata operand.
bool isMetadata() const { return OpKind == MO_Metadata; }
bool isMCSymbol() const { return OpKind == MO_MCSymbol; }
+ bool isDbgInstrRef() const { return OpKind == MO_DbgInstrRef; }
bool isCFIIndex() const { return OpKind == MO_CFIIndex; }
bool isIntrinsicID() const { return OpKind == MO_IntrinsicID; }
bool isPredicate() const { return OpKind == MO_Predicate; }
@@ -584,6 +591,16 @@ class MachineOperand {
return Contents.Sym;
}
+ unsigned getInstrRefInstrIndex() const {
+ assert(isDbgInstrRef() && "Wrong MachineOperand accessor");
+ return Contents.InstrRef.InstrIdx;
+ }
+
+ unsigned getInstrRefOpIndex() const {
+ assert(isDbgInstrRef() && "Wrong MachineOperand accessor");
+ return Contents.InstrRef.OpIdx;
+ }
+
unsigned getCFIIndex() const {
assert(isCFIIndex() && "Wrong MachineOperand accessor");
return Contents.CFIIndex;
@@ -695,6 +712,15 @@ class MachineOperand {
Contents.MD = MD;
}
+ void setInstrRefInstrIndex(unsigned InstrIdx) {
+ assert(isDbgInstrRef() && "Wrong MachineOperand mutator");
+ Contents.InstrRef.InstrIdx = InstrIdx;
+ }
+ void setInstrRefOpIndex(unsigned OpIdx) {
+ assert(isDbgInstrRef() && "Wrong MachineOperand mutator");
+ Contents.InstrRef.OpIdx = OpIdx;
+ }
+
void setMBB(MachineBasicBlock *MBB) {
assert(isMBB() && "Wrong MachineOperand mutator");
Contents.MBB = MBB;
@@ -763,6 +789,10 @@ class MachineOperand {
void ChangeToTargetIndex(unsigned Idx, int64_t Offset,
unsigned TargetFlags = 0);
+ /// Replace this operand with an Instruction Reference.
+ void ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
+ unsigned TargetFlags = 0);
+
/// ChangeToRegister - Replace this operand with a new register operand of
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
@@ -919,6 +949,13 @@ class MachineOperand {
return Op;
}
+ static MachineOperand CreateDbgInstrRef(unsigned InstrIdx, unsigned OpIdx) {
+ MachineOperand Op(MachineOperand::MO_DbgInstrRef);
+ Op.Contents.InstrRef.InstrIdx = InstrIdx;
+ Op.Contents.InstrRef.OpIdx = OpIdx;
+ return Op;
+ }
+
static MachineOperand CreateCFIIndex(unsigned CFIIndex) {
MachineOperand Op(MachineOperand::MO_CFIIndex);
Op.Contents.CFIIndex = CFIIndex;
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
index fc00b9d190536..4f45501adf96f 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
@@ -1429,8 +1429,8 @@ bool InstrRefBasedLDV::transferDebugInstrRef(MachineInstr &MI,
if (!VTracker && !TTracker)
return false;
- unsigned InstNo = MI.getOperand(0).getImm();
- unsigned OpNo = MI.getOperand(1).getImm();
+ unsigned InstNo = MI.getDebugOperand(0).getInstrRefInstrIndex();
+ unsigned OpNo = MI.getDebugOperand(0).getInstrRefOpIndex();
const DILocalVariable *Var = MI.getDebugVariable();
const DIExpression *Expr = MI.getDebugExpression();
@@ -2119,7 +2119,7 @@ bool InstrRefBasedLDV::transferRegisterCopy(MachineInstr &MI) {
/// \param MI A previously unprocessed debug instruction to analyze for
/// fragment usage.
void InstrRefBasedLDV::accumulateFragmentMap(MachineInstr &MI) {
- assert(MI.isDebugValue() || MI.isDebugRef());
+ assert(MI.isDebugValueLike());
DebugVariable MIVar(MI.getDebugVariable(), MI.getDebugExpression(),
MI.getDebugLoc()->getInlinedAt());
FragmentInfo ThisFragment = MIVar.getFragmentOrDefault();
@@ -2224,7 +2224,7 @@ void InstrRefBasedLDV::produceMLocTransferFunction(
process(MI, nullptr, nullptr);
// Also accumulate fragment map.
- if (MI.isDebugValue() || MI.isDebugRef())
+ if (MI.isDebugValueLike())
accumulateFragmentMap(MI);
// Create a map from the instruction number (if present) to the
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
index 7c986eaba4cd5..39584db4c6694 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
@@ -984,7 +984,7 @@ class VLocTracker {
void defVar(const MachineInstr &MI, const DbgValueProperties &Properties,
const SmallVectorImpl<DbgOpID> &DebugOps) {
- assert(MI.isDebugValue() || MI.isDebugRef());
+ assert(MI.isDebugValueLike());
DebugVariable Var(MI.getDebugVariable(), MI.getDebugExpression(),
MI.getDebugLoc()->getInlinedAt());
DbgValue Rec = (DebugOps.size() > 0)
diff --git a/llvm/lib/CodeGen/LiveDebugVariables.cpp b/llvm/lib/CodeGen/LiveDebugVariables.cpp
index d211536708e8c..60e6dfb451513 100644
--- a/llvm/lib/CodeGen/LiveDebugVariables.cpp
+++ b/llvm/lib/CodeGen/LiveDebugVariables.cpp
@@ -876,12 +876,16 @@ bool LDVImpl::handleDebugValue(MachineInstr &MI, SlotIndex Idx) {
MachineBasicBlock::iterator LDVImpl::handleDebugInstr(MachineInstr &MI,
SlotIndex Idx) {
- assert(MI.isDebugValue() || MI.isDebugRef() || MI.isDebugPHI());
+ assert(MI.isDebugValueLike() || MI.isDebugPHI());
// In instruction referencing mode, there should be no DBG_VALUE instructions
// that refer to virtual registers. They might still refer to constants.
- if (MI.isDebugValue())
- assert(!MI.getOperand(0).isReg() || !MI.getOperand(0).getReg().isVirtual());
+ if (MI.isDebugValueLike())
+ assert(none_of(MI.debug_operands(),
+ [](const MachineOperand &MO) {
+ return MO.isReg() && MO.getReg().isVirtual();
+ }) &&
+ "MIs should not refer to Virtual Registers in InstrRef mode.");
// Unlink the instruction, store it in the debug instructions collection.
auto NextInst = std::next(MI.getIterator());
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.cpp b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
index e9cd5fdaa0706..c9540118591bd 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.cpp
@@ -216,6 +216,7 @@ static MIToken::TokenKind getIdentifierKind(StringRef Identifier) {
.Case("nofpexcept", MIToken::kw_nofpexcept)
.Case("debug-location", MIToken::kw_debug_location)
.Case("debug-instr-number", MIToken::kw_debug_instr_number)
+ .Case("dbg-instr-ref", MIToken::kw_dbg_instr_ref)
.Case("same_value", MIToken::kw_cfi_same_value)
.Case("offset", MIToken::kw_cfi_offset)
.Case("rel_offset", MIToken::kw_cfi_rel_offset)
diff --git a/llvm/lib/CodeGen/MIRParser/MILexer.h b/llvm/lib/CodeGen/MIRParser/MILexer.h
index b1ffeac865144..31a7bfdf90777 100644
--- a/llvm/lib/CodeGen/MIRParser/MILexer.h
+++ b/llvm/lib/CodeGen/MIRParser/MILexer.h
@@ -75,6 +75,7 @@ struct MIToken {
kw_nofpexcept,
kw_debug_location,
kw_debug_instr_number,
+ kw_dbg_instr_ref,
kw_cfi_same_value,
kw_cfi_offset,
kw_cfi_rel_offset,
diff --git a/llvm/lib/CodeGen/MIRParser/MIParser.cpp b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
index 8b27edee45fe5..f87d262e044a4 100644
--- a/llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ b/llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -485,6 +485,7 @@ class MIParser {
bool parsePredicateOperand(MachineOperand &Dest);
bool parseShuffleMaskOperand(MachineOperand &Dest);
bool parseTargetIndexOperand(MachineOperand &Dest);
+ bool parseDbgInstrRefOperand(MachineOperand &Dest);
bool parseCustomRegisterMaskOperand(MachineOperand &Dest);
bool parseLiveoutRegisterMaskOperand(MachineOperand &Dest);
bool parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
@@ -2715,6 +2716,37 @@ bool MIParser::parseShuffleMaskOperand(MachineOperand &Dest) {
return false;
}
+bool MIParser::parseDbgInstrRefOperand(MachineOperand &Dest) {
+ assert(Token.is(MIToken::kw_dbg_instr_ref));
+
+ lex();
+ if (expectAndConsume(MIToken::lparen))
+ return error("expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
+
+ if (Token.isNot(MIToken::IntegerLiteral) || Token.integerValue().isNegative())
+ return error("expected unsigned integer for instruction index");
+ uint64_t InstrIdx = Token.integerValue().getZExtValue();
+ assert(InstrIdx <= std::numeric_limits<unsigned>::max() &&
+ "Instruction reference's instruction index is too large");
+ lex();
+
+ if (expectAndConsume(MIToken::comma))
+ return error("expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
+
+ if (Token.isNot(MIToken::IntegerLiteral) || Token.integerValue().isNegative())
+ return error("expected unsigned integer for operand index");
+ uint64_t OpIdx = Token.integerValue().getZExtValue();
+ assert(OpIdx <= std::numeric_limits<unsigned>::max() &&
+ "Instruction reference's operand index is too large");
+ lex();
+
+ if (expectAndConsume(MIToken::rparen))
+ return error("expected syntax dbg-instr-ref(<unsigned>, <unsigned>)");
+
+ Dest = MachineOperand::CreateDbgInstrRef(InstrIdx, OpIdx);
+ return false;
+}
+
bool MIParser::parseTargetIndexOperand(MachineOperand &Dest) {
assert(Token.is(MIToken::kw_target_index));
lex();
@@ -2866,6 +2898,8 @@ bool MIParser::parseMachineOperand(const unsigned OpCode, const unsigned OpIdx,
return parsePredicateOperand(Dest);
case MIToken::kw_shufflemask:
return parseShuffleMaskOperand(Dest);
+ case MIToken::kw_dbg_instr_ref:
+ return parseDbgInstrRefOperand(Dest);
case MIToken::Error:
return true;
case MIToken::Identifier:
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index fa29c5667cdaa..0f4a8a280bc8e 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -910,6 +910,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
case MachineOperand::MO_IntrinsicID:
case MachineOperand::MO_Predicate:
case MachineOperand::MO_BlockAddress:
+ case MachineOperand::MO_DbgInstrRef:
case MachineOperand::MO_ShuffleMask: {
unsigned TiedOperandIdx = 0;
if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
diff --git a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
index 35c9aebc119c6..d0b7dddd75397 100644
--- a/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
+++ b/llvm/lib/CodeGen/MIRVRegNamerUtils.cpp
@@ -113,6 +113,7 @@ std::string VRegRenamer::getInstructionOpcodeHash(MachineInstr &MI) {
case MachineOperand::MO_Metadata:
case MachineOperand::MO_MCSymbol:
case MachineOperand::MO_ShuffleMask:
+ case MachineOperand::MO_DbgInstrRef:
return 0;
}
llvm_unreachable("Unexpected MachineOperandType.");
diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp
index c6653ae3a6659..a7f0abc50119b 100644
--- a/llvm/lib/CodeGen/MachineFunction.cpp
+++ b/llvm/lib/CodeGen/MachineFunction.cpp
@@ -1196,19 +1196,18 @@ void MachineFunction::finalizeDebugInstrRefs() {
auto *TII = getSubtarget().getInstrInfo();
auto MakeUndefDbgValue = [&](MachineInstr &MI) {
- const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_VALUE);
+ const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_VALUE_LIST);
MI.setDesc(RefII);
- MI.getOperand(0).setReg(0);
- MI.getOperand(1).ChangeToRegister(0, false);
+ MI.getDebugOperand(0).setReg(0);
};
DenseMap<Register, DebugInstrOperandPair> ArgDbgPHIs;
for (auto &MBB : *this) {
for (auto &MI : MBB) {
- if (!MI.isDebugRef() || !MI.getOperand(0).isReg())
+ if (!MI.isDebugRef() || !MI.getDebugOperand(0).isReg())
continue;
- Register Reg = MI.getOperand(0).getReg();
+ Register Reg = MI.getDebugOperand(0).getReg();
// Some vregs can be deleted as redundant in the meantime. Mark those
// as DBG_VALUE $noreg. Additionally, some normal instructions are
@@ -1226,8 +1225,7 @@ void MachineFunction::finalizeDebugInstrRefs() {
// for why this is important.
if (DefMI.isCopyLike() || TII->isCopyInstr(DefMI)) {
auto Result = salvageCopySSA(DefMI, ArgDbgPHIs);
- MI.getOperand(0).ChangeToImmediate(Result.first);
- MI.getOperand(1).setImm(Result.second);
+ MI.getDebugOperand(0).ChangeToDbgInstrRef(Result.first, Result.second);
} else {
// Otherwise, identify the operand number that the VReg refers to.
unsigned OperandIdx = 0;
@@ -1240,8 +1238,7 @@ void MachineFunction::finalizeDebugInstrRefs() {
// Morph this instr ref to point at the given instruction and operand.
unsigned ID = DefMI.getDebugInstrNum();
- MI.getOperand(0).ChangeToImmediate(ID);
- MI.getOperand(1).setImm(OperandIdx);
+ MI.getDebugOperand(0).ChangeToDbgInstrRef(ID, OperandIdx);
}
}
}
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 11452436485b7..a54618c2d8bf7 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -675,7 +675,7 @@ bool MachineInstr::isIdenticalTo(const MachineInstr &Other,
}
bool MachineInstr::isEquivalentDbgInstr(const MachineInstr &Other) const {
- if (!isDebugValue() || !Other.isDebugValue())
+ if (!isDebugValueLike() || !Other.isDebugValueLike())
return false;
if (getDebugLoc() != Other.getDebugLoc())
return false;
@@ -854,14 +854,14 @@ const DILabel *MachineInstr::getDebugLabel() const {
}
const MachineOperand &MachineInstr::getDebugVariableOp() const {
- assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
- unsigned VariableOp = isDebugValueList() ? 0 : 2;
+ assert((isDebugValueLike()) && "not a DBG_VALUE*");
+ unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
return getOperand(VariableOp);
}
MachineOperand &MachineInstr::getDebugVariableOp() {
- assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
- unsigned VariableOp = isDebugValueList() ? 0 : 2;
+ assert((isDebugValueLike()) && "not a DBG_VALUE*");
+ unsigned VariableOp = isNonListDebugValue() ? 2 : 0;
return getOperand(VariableOp);
}
@@ -870,14 +870,14 @@ const DILocalVariable *MachineInstr::getDebugVariable() const {
}
const MachineOperand &MachineInstr::getDebugExpressionOp() const {
- assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
- unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
+ assert((isDebugValueLike()) && "not a DBG_VALUE*");
+ unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
return getOperand(ExpressionOp);
}
MachineOperand &MachineInstr::getDebugExpressionOp() {
- assert((isDebugValue() || isDebugRef()) && "not a DBG_VALUE*");
- unsigned ExpressionOp = isDebugValueList() ? 1 : 3;
+ assert((isDebugValueLike()) && "not a DBG_VALUE*");
+ unsigned ExpressionOp = isNonListDebugValue() ? 3 : 1;
return getOperand(ExpressionOp);
}
@@ -2138,41 +2138,35 @@ MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
const MCInstrDesc &MCID, bool IsIndirect,
- const MachineOperand &MO,
+ ArrayRef<MachineOperand> DebugOps,
const MDNode *Variable, const MDNode *Expr) {
assert(isa<DILocalVariable>(Variable) && "not a variable");
assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
"Expected inlined-at fields to agree");
- if (MO.isReg())
- return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
-
- auto MIB = BuildMI(MF, DL, MCID).add(MO);
- if (IsIndirect)
- MIB.addImm(0U);
- else
- MIB.addReg(0U);
- return MIB.addMetadata(Variable).addMetadata(Expr);
-}
-
-MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
- const MCInstrDesc &MCID, bool IsIndirect,
- ArrayRef<MachineOperand> MOs,
- const MDNode *Variable, const MDNode *Expr) {
- assert(isa<DILocalVariable>(Variable) && "not a variable");
- assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
- assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
- "Expected inlined-at fields to agree");
- if (MCID.Opcode == TargetOpcode::DBG_VALUE)
- return BuildMI(MF, DL, MCID, IsIndirect, MOs[0], Variable, Expr);
+ if (MCID.Opcode == TargetOpcode::DBG_VALUE) {
+ assert(DebugOps.size() == 1 &&
+ "DBG_VALUE must contain exactly one debug operand");
+ MachineOperand DebugOp = DebugOps[0];
+ if (DebugOp.isReg())
+ return BuildMI(MF, DL, MCID, IsIndirect, DebugOp.getReg(), Variable,
+ Expr);
+
+ auto MIB = BuildMI(MF, DL, MCID).add(DebugOp);
+ if (IsIndirect)
+ MIB.addImm(0U);
+ else
+ MIB.addReg(0U);
+ return MIB.addMetadata(Variable).addMetadata(Expr);
+ }
auto MIB = BuildMI(MF, DL, MCID);
MIB.addMetadata(Variable).addMetadata(Expr);
- for (const MachineOperand &MO : MOs)
- if (MO.isReg())
- MIB.addReg(MO.getReg());
+ for (const MachineOperand &DebugOp : DebugOps)
+ if (DebugOp.isReg())
+ MIB.addReg(DebugOp.getReg());
else
- MIB.add(MO);
+ MIB.add(DebugOp);
return MIB;
}
@@ -2190,21 +2184,12 @@ MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
const DebugLoc &DL, const MCInstrDesc &MCID,
- bool IsIndirect, MachineOperand &MO,
- const MDNode *Variable, const MDNode *Expr) {
- MachineFunction &MF = *BB.getParent();
- MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MO, Variable, Expr);
- BB.insert(I, MI);
- return MachineInstrBuilder(MF, *MI);
-}
-
-MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
- MachineBasicBlock::iterator I,
- const DebugLoc &DL, const MCInstrDesc &MCID,
- bool IsIndirect, ArrayRef<MachineOperand> MOs,
+ bool IsIndirect,
+ ArrayRef<MachineOperand> DebugOps,
const MDNode *Variable, const MDNode *Expr) {
MachineFunction &MF = *BB.getParent();
- MachineInstr *MI = BuildMI(MF, DL, MCID, IsIndirect, MOs, Variable, Expr);
+ MachineInstr *MI =
+ BuildMI(MF, DL, MCID, IsIndirect, DebugOps, Variable, Expr);
BB.insert(I, MI);
return MachineInstrBuilder(MF, *MI);
}
@@ -2246,6 +2231,8 @@ MachineInstr *llvm::buildDbgValueForSpill(MachineBasicBlock &BB,
MachineBasicBlock::iterator I,
const MachineInstr &Orig,
int FrameIndex, Register SpillReg) {
+ assert(!Orig.isDebugRef() &&
+ "DBG_INSTR_REF should not reference a virtual register.");
const DIExpression *Expr = computeExprForSpill(Orig, SpillReg);
MachineInstrBuilder NewMI =
BuildMI(BB, I, Orig.getDebugLoc(), Orig.getDesc());
diff --git a/llvm/lib/CodeGen/MachineOperand.cpp b/llvm/lib/CodeGen/MachineOperand.cpp
index a3ffce905b67b..62b7f776f165f 100644
--- a/llvm/lib/CodeGen/MachineOperand.cpp
+++ b/llvm/lib/CodeGen/MachineOperand.cpp
@@ -236,6 +236,19 @@ void MachineOperand::ChangeToTargetIndex(unsigned Idx, int64_t Offset,
setTargetFlags(TargetFlags);
}
+void MachineOperand::ChangeToDbgInstrRef(unsigned InstrIdx, unsigned OpIdx,
+ unsigned TargetFlags) {
+ assert((!isReg() || !isTied()) &&
+ "Cannot change a tied operand into a DbgInstrRef");
+
+ removeRegFromUses();
+
+ OpKind = MO_DbgInstrRef;
+ setInstrRefInstrIndex(InstrIdx);
+ setInstrRefOpIndex(OpIdx);
+ setTargetFlags(TargetFlags);
+}
+
/// ChangeToRegister - Replace this operand with a new register operand of
/// the specified value. If an operand is known to be an register already,
/// the setReg method should be used.
@@ -337,6 +350,9 @@ bool MachineOperand::isIdenticalTo(const MachineOperand &Other) const {
}
case MachineOperand::MO_MCSymbol:
return getMCSymbol() == Other.getMCSymbol();
+ case MachineOperand::MO_DbgInstrRef:
+ return getInstrRefInstrIndex() == Other.getInstrRefInstrIndex() &&
+ getInstrRefOpIndex() == Other.getInstrRefOpIndex();
case MachineOperand::MO_CFIIndex:
return getCFIIndex() == Other.getCFIIndex();
case MachineOperand::MO_Metadata:
@@ -401,6 +417,9 @@ hash_code llvm::hash_value(const MachineOperand &MO) {
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMetadata());
case MachineOperand::MO_MCSymbol:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getMCSymbol());
+ case MachineOperand::MO_DbgInstrRef:
+ return hash_combine(MO.getType(), MO.getTargetFlags(),
+ MO.getInstrRefInstrIndex(), MO.getInstrRefOpIndex());
case MachineOperand::MO_CFIIndex:
return hash_combine(MO.getType(), MO.getTargetFlags(), MO.getCFIIndex());
case MachineOperand::MO_IntrinsicID:
@@ -942,6 +961,11 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST,
case MachineOperand::MO_MCSymbol:
printSymbol(OS, *getMCSymbol());
break;
+ case MachineOperand::MO_DbgInstrRef: {
+ OS << "dbg-instr-ref(" << getInstrRefInstrIndex() << ", "
+ << getInstrRefOpIndex() << ')';
+ break;
+ }
case MachineOperand::MO_CFIIndex: {
if (const MachineFunction *MF = getMFIfAvailable(*this))
printCFI(OS, MF->getFrameInstructions()[getCFIIndex()], TRI);
diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp
index 0568bc6a46008..66e5c22062efa 100644
--- a/llvm/lib/CodeGen/MachineSink.cpp
+++ b/llvm/lib/CodeGen/MachineSink.cpp
@@ -1779,7 +1779,7 @@ bool PostRAMachineSinking::tryToSinkCopy(MachineBasicBlock &CurBB,
// We must sink this DBG_VALUE if its operand is sunk. To avoid searching
// for DBG_VALUEs later, record them when they're encountered.
- if (MI.isDebugValue()) {
+ if (MI.isDebugValue() && !MI.isDebugRef()) {
SmallDenseMap<MCRegister, SmallVector<unsigned, 2>, 4> MIUnits;
bool IsValid = true;
for (MachineOperand &MO : MI.debug_operands()) {
diff --git a/llvm/lib/CodeGen/MachineStableHash.cpp b/llvm/lib/CodeGen/MachineStableHash.cpp
index 941aeaf15f320..b1a2a29f07b47 100644
--- a/llvm/lib/CodeGen/MachineStableHash.cpp
+++ b/llvm/lib/CodeGen/MachineStableHash.cpp
@@ -165,6 +165,9 @@ stable_hash llvm::stableHashValue(const MachineOperand &MO) {
case MachineOperand::MO_Predicate:
return stable_hash_combine(MO.getType(), MO.getTargetFlags(),
MO.getPredicate());
+ case MachineOperand::MO_DbgInstrRef:
+ return stable_hash_combine(MO.getType(), MO.getInstrRefInstrIndex(),
+ MO.getInstrRefOpIndex());
}
llvm_unreachable("Invalid machine operand type");
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
index 704c41b656b54..af51223554728 100644
--- a/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -1252,22 +1252,21 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
if (Op) {
assert(DI->getVariable()->isValidLocationForIntrinsic(MIMD.getDL()) &&
"Expected inlined-at fields to agree");
- // A dbg.declare describes the address of a source variable, so lower it
- // into an indirect DBG_VALUE.
- auto Builder =
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(),
- TII.get(TargetOpcode::DBG_VALUE), /*IsIndirect*/ true, *Op,
- DI->getVariable(), DI->getExpression());
-
- // If using instruction referencing, mutate this into a DBG_INSTR_REF,
- // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto
- // the expression, we don't have an "indirect" flag in DBG_INSTR_REF.
if (UseInstrRefDebugInfo && Op->isReg()) {
- Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF));
- Builder->getOperand(1).ChangeToImmediate(0);
+ // If using instruction referencing, produce this as a DBG_INSTR_REF,
+ // to be later patched up by finalizeDebugInstrRefs. Tack a deref onto
+ // the expression, we don't have an "indirect" flag in DBG_INSTR_REF.
auto *NewExpr =
DIExpression::prepend(DI->getExpression(), DIExpression::DerefBefore);
- Builder->getOperand(3).setMetadata(NewExpr);
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(),
+ TII.get(TargetOpcode::DBG_INSTR_REF), /*IsIndirect*/ false, *Op,
+ DI->getVariable(), NewExpr);
+ } else {
+ // A dbg.declare describes the address of a source variable, so lower it
+ // into an indirect DBG_VALUE.
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(),
+ TII.get(TargetOpcode::DBG_VALUE), /*IsIndirect*/ true, *Op,
+ DI->getVariable(), DI->getExpression());
}
} else {
// We can't yet handle anything else here because it would require
@@ -1314,16 +1313,21 @@ bool FastISel::selectIntrinsicCall(const IntrinsicInst *II) {
.addMetadata(DI->getExpression());
} else if (Register Reg = lookUpRegForValue(V)) {
// FIXME: This does not handle register-indirect values at offset 0.
- bool IsIndirect = false;
- auto Builder =
- BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(), II,
- IsIndirect, Reg, DI->getVariable(), DI->getExpression());
-
- // If using instruction referencing, mutate this into a DBG_INSTR_REF,
- // to be later patched up by finalizeDebugInstrRefs.
- if (UseInstrRefDebugInfo) {
- Builder->setDesc(TII.get(TargetOpcode::DBG_INSTR_REF));
- Builder->getOperand(1).ChangeToImmediate(0);
+ if (!UseInstrRefDebugInfo) {
+ bool IsIndirect = false;
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(), II, IsIndirect,
+ Reg, DI->getVariable(), DI->getExpression());
+ } else {
+ // If using instruction referencing, produce this as a DBG_INSTR_REF,
+ // to be later patched up by finalizeDebugInstrRefs.
+ SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg(
+ /* Reg */ Reg, /* isDef */ false, /* isImp */ false,
+ /* isKill */ false, /* isDead */ false,
+ /* isUndef */ false, /* isEarlyClobber */ false,
+ /* SubReg */ 0, /* isDebug */ true)});
+ BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD.getDL(),
+ TII.get(TargetOpcode::DBG_INSTR_REF), /*IsIndirect*/ false, MOs,
+ DI->getVariable(), DI->getExpression());
}
} else {
// We don't know how to handle other cases, so we drop.
diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
index e2e5158d73982..e37eb7e4cd0f5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -794,12 +794,12 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
// i.e., point the instruction at the vreg, and patch it up later in
// MachineFunction::finalizeDebugInstrRefs.
auto EmitHalfDoneInstrRef = [&](unsigned VReg) -> MachineInstr * {
- auto MIB = BuildMI(*MF, DL, RefII);
- MIB.addReg(VReg);
- MIB.addImm(0);
- MIB.addMetadata(Var);
- MIB.addMetadata(Expr);
- return MIB;
+ SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg(
+ /* Reg */ VReg, /* isDef */ false, /* isImp */ false,
+ /* isKill */ false, /* isDead */ false,
+ /* isUndef */ false, /* isEarlyClobber */ false,
+ /* SubReg */ 0, /* isDebug */ true)});
+ return BuildMI(*MF, DL, RefII, false, MOs, Var, Expr);
};
// Try to find both the defined register and the instruction defining it.
@@ -842,8 +842,6 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
if (DefMI->isCopyLike() || TII->isCopyInstr(*DefMI))
return EmitHalfDoneInstrRef(VReg);
- auto MIB = BuildMI(*MF, DL, RefII);
-
// Find the operand number which defines the specified VReg.
unsigned OperandIdx = 0;
for (const auto &MO : DefMI->operands()) {
@@ -855,11 +853,9 @@ InstrEmitter::EmitDbgInstrRef(SDDbgValue *SD,
// Make the DBG_INSTR_REF refer to that instruction, and that operand.
unsigned InstrNum = DefMI->getDebugInstrNum();
- MIB.addImm(InstrNum);
- MIB.addImm(OperandIdx);
- MIB.addMetadata(Var);
- MIB.addMetadata(Expr);
- return &*MIB;
+ SmallVector<MachineOperand, 1> MOs(
+ {MachineOperand::CreateDbgInstrRef(InstrNum, OperandIdx)});
+ return BuildMI(*MF, DL, RefII, false, MOs, Var, Expr);
}
MachineInstr *InstrEmitter::EmitDbgNoLocation(SDDbgValue *SD) {
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 4d44e962c8cfb..1b514231fa844 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -5579,17 +5579,18 @@ bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
// For VRegs, in instruction referencing mode, create a DBG_INSTR_REF
// pointing at the VReg, which will be patched up later.
auto &Inst = TII->get(TargetOpcode::DBG_INSTR_REF);
- auto MIB = BuildMI(MF, DL, Inst);
- MIB.addReg(Reg);
- MIB.addImm(0);
- MIB.addMetadata(Variable);
+ SmallVector<MachineOperand, 1> MOs({MachineOperand::CreateReg(
+ /* Reg */ Reg, /* isDef */ false, /* isImp */ false,
+ /* isKill */ false, /* isDead */ false,
+ /* isUndef */ false, /* isEarlyClobber */ false,
+ /* SubReg */ 0, /* isDebug */ true)});
+
auto *NewDIExpr = FragExpr;
// We don't have an "Indirect" field in DBG_INSTR_REF, fold that into
// the DIExpression.
if (Indirect)
NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore);
- MIB.addMetadata(NewDIExpr);
- return MIB;
+ return BuildMI(MF, DL, Inst, false, MOs, Variable, NewDIExpr);
} else {
// Create a completely standard DBG_VALUE.
auto &Inst = TII->get(TargetOpcode::DBG_VALUE);
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 8b03b714fbb39..d8be270ce8475 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -551,9 +551,9 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
MachineInstr *MI = FuncInfo->ArgDbgValues[e - i - 1];
assert(MI->getOpcode() != TargetOpcode::DBG_VALUE_LIST &&
"Function parameters should not be described by DBG_VALUE_LIST.");
- bool hasFI = MI->getOperand(0).isFI();
+ bool hasFI = MI->getDebugOperand(0).isFI();
Register Reg =
- hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
+ hasFI ? TRI.getFrameRegister(*MF) : MI->getDebugOperand(0).getReg();
if (Register::isPhysicalRegister(Reg))
EntryMBB->insert(EntryMBB->begin(), MI);
else {
@@ -583,7 +583,7 @@ bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) {
DebugLoc DL = MI->getDebugLoc();
bool IsIndirect = MI->isIndirectDebugValue();
if (IsIndirect)
- assert(MI->getOperand(1).getImm() == 0 &&
+ assert(MI->getDebugOffset().getImm() == 0 &&
"DBG_VALUE with nonzero offset");
assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
"Expected inlined-at fields to agree");
diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
index e5347ed8e53a4..960adc80d71ab 100644
--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -953,6 +953,7 @@ static bool IsAnAddressOperand(const MachineOperand &MO) {
case MachineOperand::MO_Metadata:
case MachineOperand::MO_MCSymbol:
return true;
+ case MachineOperand::MO_DbgInstrRef:
case MachineOperand::MO_CFIIndex:
return false;
case MachineOperand::MO_IntrinsicID:
diff --git a/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir b/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
index 124e1ecb37896..cfda97f77874f 100644
--- a/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
+++ b/llvm/test/CodeGen/X86/dbg-value-superreg-copy2.mir
@@ -39,7 +39,7 @@ body: |
%0:gr16_abcd = MOV16ri 1, debug-instr-number 1, debug-location !9
bb.1:
- DBG_INSTR_REF 2, 0, !7, !DIExpression(), debug-location !9
+ DBG_INSTR_REF !7, !DIExpression(), dbg-instr-ref(2, 0), debug-location !9
%1:gr16 = COPY %0, debug-location !9
%2:gr16 = COPY %0
diff --git a/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir b/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
index 960c5c997600c..237177213590f 100644
--- a/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
+++ b/llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
@@ -298,8 +298,8 @@ body: |
$rcx = CMOV64rr killed $rcx, killed $rdx, 5, implicit killed $eflags
$rcx = OR64rr killed $rcx, killed $rsi, implicit-def dead $eflags
$rdx = MOVSX64rm32 $rbx, 1, $noreg, 0, $noreg :: (load (s32), align 8)
- DBG_INSTR_REF 1, 0, !46, !17, debug-location !48
- DBG_INSTR_REF 2, 0, !39, !17, debug-location !44
+ DBG_INSTR_REF !46, !17, dbg-instr-ref(1, 0), debug-location !48
+ DBG_INSTR_REF !39, !17, dbg-instr-ref(2, 0), debug-location !44
TEST32mr killed $rcx, 4, killed $rdx, 0, $noreg, killed $eax, implicit-def $eflags :: (load (s32))
JCC_1 %bb.2, 5, implicit $eflags
JMP_1 %bb.3
diff --git a/llvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll b/llvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll
index 93a7e009a4584..5daf5fe64a68a 100644
--- a/llvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll
+++ b/llvm/test/DebugInfo/AArch64/instr-ref-const-physreg.ll
@@ -7,7 +7,7 @@
; crash, and we don't just drop the information.
; CHECK: DBG_PHI $xzr, 1
-; CHECK: DBG_INSTR_REF 1, 0
+; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
define i64 @test() !dbg !7 {
%foo = add i64 0, 0
diff --git a/llvm/test/DebugInfo/ARM/instr-ref-tcreturn.ll b/llvm/test/DebugInfo/ARM/instr-ref-tcreturn.ll
index eeab02e59c06c..ee49a764acc64 100644
--- a/llvm/test/DebugInfo/ARM/instr-ref-tcreturn.ll
+++ b/llvm/test/DebugInfo/ARM/instr-ref-tcreturn.ll
@@ -25,7 +25,7 @@ target triple = "thumbv7-apple-ios7.0.0"
; CHECK-LABEL: bb.1.entry:
; CHECK: $r0 = COPY %0
; CHECK-NEXT: $r1 = COPY %1
-; CHECK-NEXT: DBG_INSTR_REF 1, 0
+; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: TCRETURNdi &__divsi3, 0, csr_ios, implicit $sp, implicit $r0, implicit $r1
declare i1 @ext()
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir b/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir
index 016db912107c4..d6186bd2cacaa 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/accept-nonlive-reg-phis.mir
@@ -80,7 +80,7 @@ body: |
bb.0.entry:
DBG_PHI $fp0, 3
- DBG_INSTR_REF 3, 0, !17, !DIExpression(), debug-location !30
+ DBG_INSTR_REF !17, !DIExpression(), dbg-instr-ref(3, 0), debug-location !30
$eax = MOV32ri 0
RET 0, debug-location !36
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir
index 0e105c132001a..f1841072cc798 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phi-subregister-location.mir
@@ -9,7 +9,7 @@
#
# CHECK-LABEL: name: foo
# CHECK: DBG_PHI $edi
-# CHECK-NEXT: DBG_INSTR_REF 2, 0
+# CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
# CHECK-NEXT: DBG_VALUE $dil
--- |
; ModuleID = 'out.ll'
@@ -63,7 +63,7 @@ body: |
liveins: $edi
DBG_PHI $edi, 1
- DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
renamable $rax = MOV64rm $rip, 1, $noreg, target-flags(x86-gotpcrel) @someglobal, $noreg, debug-location !13 :: (load (s64) from got)
MOV8mr killed renamable $rax, 1, $noreg, 0, $noreg, renamable $dil, debug-location !13 :: (store (s8) into @someglobal)
RET64 debug-location !13
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir
index 0102f648c27a9..1ff3b2d1272ea 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv.mir
@@ -134,7 +134,7 @@ body: |
DBG_PHI $rbx, 1
$rax = COPY $rbx
$rbx = MOV64ri 0
- DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
; This sequence should mark the contents of rbx on block entry as being the
; value for the variable at this DBG_INSTR_REF. We've force it to be in
@@ -142,7 +142,7 @@ body: |
; CHECK: DBG_PHI $rbx, 1
; CHECK-NEXT: $rax = COPY $rbx
; CHECK-NEXT: $rbx = MOV64ri 0
- ; CHECK-NEXT: DBG_INSTR_REF 1, 0
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $rax, $noreg
$rbx = COPY $rax
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir
index ac42364ae22f5..e6118ab249fcf 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-in-ldv2.mir
@@ -84,8 +84,8 @@ body: |
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
;; This should resolve to the loaded register.
- DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
- ; CHECK: DBG_INSTR_REF 1, 0,
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $rcx
;; And if we say it's a smaller size, we should be able to pick out smaller
@@ -96,8 +96,8 @@ body: |
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
;; This should pick out the 32 bit value.
- DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
- ; CHECK: DBG_INSTR_REF 2, 0,
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $ecx
;; Try all the other subregs.
@@ -106,8 +106,8 @@ body: |
$rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
- DBG_INSTR_REF 3, 0, !12, !DIExpression(), debug-location !13
- ; CHECK: DBG_INSTR_REF 3, 0,
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(3, 0), debug-location !13
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; CHECK-NEXT: DBG_VALUE $cx
DBG_PHI %stack.0, 4, 8
@@ -115,8 +115,8 @@ body: |
$rcx = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
- DBG_INSTR_REF 4, 0, !12, !DIExpression(), debug-location !13
- ; CHECK: DBG_INSTR_REF 4, 0,
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(4, 0), debug-location !13
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
; CHECK-NEXT: DBG_VALUE $cl
;; We can't, at this time, describe subregister fields with nonzero offset.
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir
index 586b4b1824331..d02d2a6c1512f 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-merging-in-ldv.mir
@@ -158,31 +158,31 @@ body: |
bb.3.if.end:
liveins: $rbx, $r14
- DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !13
- DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
- DBG_INSTR_REF 3, 0, !12, !DIExpression(), debug-location !13
+ DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(3, 0), debug-location !13
; Value number 1 is live-through the above control flow from the two
; DBG_PHIs:
- ; CHECK: DBG_INSTR_REF 1, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $r14
;
; While value number 2 has
diff erent defs that merge on entry to bb.3.
; These are both in $rbx though, and we should find its location:
- ; CHECK: DBG_INSTR_REF 2, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $rbx
;
; Value number 3 cannot be resolved because $rax is clobbered in bb.2,
; meaning the merged value in bb.3 is incorrect. It should produce a
; DBG_VALUE $noreg.
- ; CHECK: DBG_INSTR_REF 3, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; CHECK-NEXT: DBG_VALUE $noreg
renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !28
- DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
; After clobbering rbx, the variable location should not be available.
- ; CHECK: DBG_INSTR_REF 2, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $noreg
$rdi = MOV64rr $rbx, debug-location !29
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir
index 1f9843b552517..05bdd37312020 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/dbg-phis-with-loops.mir
@@ -164,31 +164,31 @@ body: |
bb.4:
liveins: $rbx, $r14
- DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !13
- DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
- DBG_INSTR_REF 3, 0, !12, !DIExpression(), debug-location !13
+ DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(3, 0), debug-location !13
; Value number 1 is live-through the above control flow from the two
; DBG_PHIs:
- ; CHECK: DBG_INSTR_REF 1, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $r14
;
; While value number 2 has
diff erent defs that merge on entry to bb.3.
; These are both in $rbx though, and we should find its location:
- ; CHECK: DBG_INSTR_REF 2, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $rbx
;
; Value number 3 cannot be resolved because $rax is clobbered in bb.2,
; meaning the merged value in bb.3 is incorrect. It should produce a
; DBG_VALUE $noreg.
- ; CHECK: DBG_INSTR_REF 3, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; CHECK-NEXT: DBG_VALUE $noreg
renamable $rbx = ADD64rr killed renamable $rbx, killed renamable $r14, implicit-def $eflags, debug-location !28
- DBG_INSTR_REF 2, 0, !12, !DIExpression(), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(2, 0), debug-location !13
; After clobbering rbx, the variable location should not be available.
- ; CHECK: DBG_INSTR_REF 2, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $noreg
$rdi = MOV64rr $rbx, debug-location !29
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir b/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir
index 2a43902cef024..0fcf5d85f3ead 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/deref-spills-with-size.mir
@@ -168,7 +168,7 @@ body: |
;; the size of the value on the stack makes it through to the expression.
$al = MOV8ri 0, debug-instr-number 1, debug-location !7
- DBG_INSTR_REF 1, 0, !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), dbg-instr-ref(1, 0), debug-location !7
; CHECK: DBG_VALUE $al, $noreg, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed,
; CHECK-SAME : DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value)
@@ -189,7 +189,7 @@ body: |
;; Try again, but with the value originating on the stack, to ensure that
;; we can find its size. It should be deref_size 1 again.
INC8m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 2, debug-location !7 :: (store (s8) into %stack.0)
- DBG_INSTR_REF 2, 1000000, !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_convert, 8, DW_ATE_signed, DW_OP_LLVM_convert, 32, DW_ATE_signed, DW_OP_stack_value), dbg-instr-ref(2, 1000000), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus,
; CHECK-SAME: DW_OP_deref_size, 1, DW_OP_LLVM_convert, 8, DW_ATE_signed,
@@ -209,7 +209,7 @@ body: |
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$eax = MOV32ri 0, debug-location !7
- DBG_INSTR_REF 7, 0, !8, !DIExpression(), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(7, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value)
@@ -217,7 +217,7 @@ body: |
;; And for when the DBG_PHI specifies a stack size...
DBG_PHI %stack.0, 8, 16
- DBG_INSTR_REF 8, 0, !8, !DIExpression(), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(8, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 2, DW_OP_stack_value)
@@ -237,7 +237,7 @@ body: |
$rax = MOV64ri 0, debug-instr-number 10, debug-location !7
MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 10, 0, !8, !DIExpression(), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(10, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_stack_value),
$eax = MOV32ri 0, debug-location !7
@@ -248,7 +248,7 @@ body: |
$eax = MOV32ri 0, debug-instr-number 11, debug-location !7
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 11, 0, !8, !DIExpression(), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(11, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, 0, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus),
$eax = MOV32ri 0, debug-location !7
@@ -259,7 +259,7 @@ body: |
$al = MOV8ri 0, debug-instr-number 12, debug-location !7
MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 12, 0, !8, !DIExpression(), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(12, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value),
$eax = MOV32ri 0, debug-location !7
@@ -270,7 +270,7 @@ body: |
$rax = MOV64ri 0, debug-instr-number 13, debug-location !7
MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 13, 0, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
+ DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(13, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
$eax = MOV32ri 0, debug-location !7
@@ -281,7 +281,7 @@ body: |
$eax = MOV32ri 0, debug-instr-number 14, debug-location !7
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 14, 0, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
+ DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(14, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, 0, ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_LLVM_fragment, 0, 32),
$eax = MOV32ri 0, debug-location !7
@@ -292,7 +292,7 @@ body: |
$al = MOV8ri 0, debug-instr-number 15, debug-location !7
MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 15, 0, !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), debug-location !7
+ DBG_INSTR_REF !10, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(15, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
$eax = MOV32ri 0, debug-location !7
@@ -305,7 +305,7 @@ body: |
$rax = MOV64ri 0, debug-instr-number 16, debug-location !7
MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 16, 0, !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), dbg-instr-ref(16, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value),
$eax = MOV32ri 0, debug-location !7
@@ -316,7 +316,7 @@ body: |
$eax = MOV32ri 0, debug-instr-number 17, debug-location !7
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 17, 0, !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), dbg-instr-ref(17, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value),
$eax = MOV32ri 0, debug-location !7
@@ -327,7 +327,7 @@ body: |
$al = MOV8ri 0, debug-instr-number 18, debug-location !7
MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 18, 0, !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value), dbg-instr-ref(18, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value),
$eax = MOV32ri 0, debug-location !7
@@ -338,7 +338,7 @@ body: |
$rax = MOV64ri 0, debug-instr-number 19, debug-location !7
MOV64mr $rsp, 1, $noreg, -8, $noreg, renamable $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 19, 0, !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), debug-location !7
+ DBG_INSTR_REF !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(19, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 8, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
$eax = MOV32ri 0, debug-location !7
@@ -349,7 +349,7 @@ body: |
$eax = MOV32ri 0, debug-instr-number 20, debug-location !7
MOV32mr $rsp, 1, $noreg, -8, $noreg, renamable $eax :: (store 4 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 20, 0, !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), debug-location !7
+ DBG_INSTR_REF !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(20, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 4, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
$eax = MOV32ri 0, debug-location !7
@@ -360,7 +360,7 @@ body: |
$al = MOV8ri 0, debug-instr-number 21, debug-location !7
MOV8mr $rsp, 1, $noreg, -8, $noreg, renamable $al :: (store 1 into %stack.0)
$rax = MOV64ri 0, debug-location !7
- DBG_INSTR_REF 21, 0, !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), debug-location !7
+ DBG_INSTR_REF !10, !DIExpression(DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(21, 0), debug-location !7
; CHECK: DBG_VALUE $rsp, $noreg, ![[VARNUM2]],
; CHECK-SAME: !DIExpression(DW_OP_constu, 8, DW_OP_minus, DW_OP_deref_size, 1, DW_OP_constu, 1, DW_OP_plus, DW_OP_stack_value, DW_OP_LLVM_fragment, 0, 32),
$eax = MOV32ri 0, debug-location !7
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
index c66c9d05c0637..516c4fbafacfd 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
@@ -302,7 +302,7 @@ body: |
MOV64mr undef renamable $rax, 1, $noreg, 0, $noreg, killed renamable $r10, debug-location !7 :: (store 8 into `%"class.llvm::Loop"*** undef`)
MOV64mr killed renamable $rdi, 1, $noreg, 40, $noreg, killed renamable $r9, debug-location !7 :: (store 8 into %ir.24)
renamable $rax = MOV64rm killed renamable $rsi, 1, $noreg, 24, $noreg, debug-location !7 :: (load 8 from %ir.26)
- DBG_INSTR_REF 1, 0, !8, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !7
renamable $rax = SUB64rr killed renamable $rax, killed renamable $r11, implicit-def dead $eflags, debug-location !7
renamable $r8 = SUB64rr killed renamable $r8, killed renamable $r14, implicit-def dead $eflags, debug-location !7
renamable $r8 = exact SAR64ri killed renamable $r8, 3, implicit-def dead $eflags, debug-location !7
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
index 53e9148bf5505..a8435d8a20795 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_illegal_locs.mir
@@ -45,36 +45,36 @@ body: |
; CHECK-LABE: bb.0.entry:
$rax = MOV64ri 1, debug-instr-number 1, debug-location !17
- DBG_INSTR_REF 1, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(1, 0), debug-location !17
;; First check that picking out location works as usual.
- ; CHECK: DBG_INSTR_REF 1, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $rax
$rax = MOV64ri 1, debug-instr-number 2, debug-location !17
- DBG_INSTR_REF 2, 999, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(2, 999), debug-location !17
;; Test out of bounds operand number.
- ; CHECK: DBG_INSTR_REF 2, 999
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 999)
; CHECK-NEXT: DBG_VALUE $noreg
$rax = MOV64ri 1, debug-instr-number 3, debug-location !17
- DBG_INSTR_REF 3, 1, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(3, 1), debug-location !17
;; Test non-register operand
- ; CHECK: DBG_INSTR_REF 3, 1
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 1)
; CHECK-NEXT: DBG_VALUE $noreg
;; FIXME: We should test what happens when this meta-instruction is seen
;; by livedbugvalues with an instruction number. However, right now it's
;; impossible to turn the machine-code verifier off when loading MIR?
;KILL implicit killed $eflags, debug-instr-number 4, debug-location !17
- ;DBG_INSTR_REF 4, 0, !16, !DIExpression(), debug-location !17
+ ;DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(4, 0), debug-location !17
;;; Test non-def operand
- ;; check: DBG_INSTR_REF 4, 0
+ ;; check: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
;; check-next: DBG_VALUE $noreg
$noreg = MOV32ri 1, debug-instr-number 5, debug-location !17
- DBG_INSTR_REF 5, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(5, 0), debug-location !17
;; Def of $noreg?
- ; CHECK: DBG_INSTR_REF 5, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
; CHECK-NEXT: DBG_VALUE $noreg
JCC_1 %bb.1, 1, implicit $eflags
@@ -85,9 +85,9 @@ body: |
; CHECK-LABEL: bb.1:
DBG_PHI $rax, 6
- DBG_INSTR_REF 6, 1, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(6, 1), debug-location !17
;; Test out-of-bounds reference to a DBG_PHI.
- ; CHECK: DBG_INSTR_REF 6, 1
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 1)
; CHECK-NEXT: DBG_VALUE $noreg
DBG_PHI $noreg, 7
@@ -97,10 +97,10 @@ body: |
successors: %bb.3
; CHECK-LABEL: bb.2:
DBG_PHI 1, 6
- DBG_INSTR_REF 6, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(6, 0), debug-location !17
;; Test non-reg operand to DBG_PHI. It's not clear if this can ever happen
;; as the result of an optimisation, but lets test for it anyway.
- ; CHECK: DBG_INSTR_REF 6, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
; CHECK-NEXT: DBG_VALUE $noreg
DBG_PHI 1, 7
@@ -108,10 +108,10 @@ body: |
bb.3:
; CHECK-LABEL: bb.3:
- DBG_INSTR_REF 7, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(7, 0), debug-location !17
;; PHI resolution of illegal inputs shouldn't crash either. It should also
;; come out as a $noreg location.
- ; CHECK: DBG_INSTR_REF 7, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
; CHECK-NEXT: DBG_VALUE $noreg
RET 0, debug-location !17
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
index 19353dae26080..9ec72ca2a5465 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir
@@ -37,14 +37,14 @@ body: |
bb.0.entry:
$rax = MOV64ri 1, debug-instr-number 1, debug-location !17
; This debug instruction should identify the value as being in $rax.
- DBG_INSTR_REF 1, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(1, 0), debug-location !17
; CHECK: DBG_VALUE $rax, $noreg
$rbx = COPY killed $rax, debug-location !17
$rax = MOV64ri 1, debug-location !17
; CHECK: DBG_VALUE $rbx, $noreg
- DBG_INSTR_REF 2, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(2, 0), debug-location !17
; No instruction is labelled with the number "2". This should produce an
; empty variable location.
; CHECK: DBG_VALUE $noreg, $noreg
@@ -56,7 +56,7 @@ body: |
; CHECK-LABEL: bb.1:
bb.1:
- DBG_INSTR_REF 3, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(3, 0), debug-location !17
; This refers to a value def'd in a parent block -- but it should be
; tracked into this block.
; CHECK: DBG_VALUE $rbx, $noreg
@@ -68,7 +68,7 @@ body: |
; any successor blocks.
; CHECK: DBG_VALUE $rbx, $noreg
- DBG_INSTR_REF 5, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(5, 0), debug-location !17
; This is a debug use-before-def: the value appears a few instructions
; later. Any earlier value should be terminated here, _and_ we should
; emit a DBG_VALUE when the value becomes available.
@@ -80,7 +80,7 @@ body: |
; CHECK: DBG_VALUE $rcx, $noreg
$rax = MOV64ri 1, debug-location !17
- DBG_INSTR_REF 6, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(6, 0), debug-location !17
; Another debug use-before-def, but across block boundaries.
; CHECK: DBG_VALUE $noreg, $noreg
JMP_1 %bb.3
@@ -104,7 +104,7 @@ body: |
$rdx = MOV64ri 1, implicit-def $eflags, debug-location !17
JCC_1 %bb.6, 4, implicit $eflags, debug-location !17
bb.5:
- DBG_INSTR_REF 7, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(7, 0), debug-location !17
; CHECK: DBG_VALUE $noreg, $noreg
JMP_1 %bb.6, debug-location !17
bb.6:
@@ -114,7 +114,7 @@ body: |
; A use-before-def shouldn't pass another definition of the variable location
; or value.
bb.7:
- DBG_INSTR_REF 8, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(8, 0), debug-location !17
; CHECK: DBG_VALUE $noreg, $noreg
DBG_VALUE $rax, $noreg, !16, !DIExpression(), debug-location !17
; CHECK: DBG_VALUE $rax, $noreg,
@@ -123,7 +123,7 @@ body: |
; Loops: use-before-defs should be live-through loops, assuming that nothing
; in that loop modifies the variable location.
bb.8:
- DBG_INSTR_REF 9, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(9, 0), debug-location !17
; CHECK: DBG_VALUE $noreg, $noreg
JCC_1 %bb.8, 4, implicit $eflags
bb.9:
@@ -135,14 +135,14 @@ body: |
bb.10:
; live-in,
; CHECK: DBG_VALUE $rax, $noreg,
- DBG_INSTR_REF 10, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(10, 0), debug-location !17
; CHECK: DBG_VALUE $noreg, $noreg
bb.11:
$rbx = MOV64ri 1, debug-location !17
bb.12:
- DBG_INSTR_REF 9, 0, !16, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !16, !DIExpression(), dbg-instr-ref(9, 0), debug-location !17
; This still has a value in $rax,
; CHECK: DBG_VALUE $rax, $noreg
JCC_1 %bb.11, 4, implicit $eflags
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
index 327fdeed7cb10..f6c53a77e68a7 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_stackslot_subregs.mir
@@ -49,7 +49,7 @@ body: |
$rax = MOV64ri 0
$rdi = MOV64ri 0
- DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
; CHECK: DBG_INSTR_REF
; CHECK-NEXT: DBG_VALUE $esi
RET64 $rsi, debug-location !12
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
index 6277b1b6dee23..615585bc43f6e 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_subreg_substitutions.mir
@@ -71,38 +71,38 @@ body: |
liveins: $rdi, $rax
CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, implicit-def $rax, debug-instr-number 4, debug-location !12
; CHECK: CALL64pcrel32
- DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
- ; CHECK-NEXT: DBG_INSTR_REF 1, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $al
- DBG_INSTR_REF 5, 0, !11, !DIExpression(), debug-location !12
- ; CHECK-NEXT: DBG_INSTR_REF 5, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(5, 0), debug-location !12
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
; CHECK-NEXT: DBG_VALUE $ah
- DBG_INSTR_REF 8, 0, !11, !DIExpression(), debug-location !12
- ; CHECK-NEXT: DBG_INSTR_REF 8, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(8, 0), debug-location !12
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(8, 0)
; CHECK-NEXT: DBG_VALUE $ah
- DBG_INSTR_REF 13, 0, !11, !DIExpression(), debug-location !12
- ; CHECK-NEXT: DBG_INSTR_REF 13, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(13, 0), debug-location !12
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(13, 0)
; CHECK-NEXT: DBG_VALUE $noreg
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !12
; CHECK: $rax = MOV64ri 0
; The value is now located in a spill slot, as a subregister within the
; slot, which InstrRefBasedLDV should be able to find.
- DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
- ; CHECK-NEXT: DBG_INSTR_REF 1, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $rsp, 0, !{{[0-9]*}}, !DIExpression(DW_OP_constu, 8, DW_OP_minus)
- DBG_INSTR_REF 5, 0, !11, !DIExpression(), debug-location !12
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(5, 0), debug-location !12
; This and the next DBG_INSTR_REF refer to a value that is on the stack, but
; is located at a non-zero offset from the start of the slot -- $ah within
; $rax is 8 bits in. Today, InstrRefBasedLDV can't express this. It also
; doesn't seem likely to be profitable.
- ; CHECK-NEXT: DBG_INSTR_REF 5, 0
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
; CHECK-NEXT: DBG_VALUE $noreg
- DBG_INSTR_REF 8, 0, !11, !DIExpression(), debug-location !12
- ; CHECK-NEXT: DBG_INSTR_REF 8, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(8, 0), debug-location !12
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(8, 0)
; CHECK-NEXT: DBG_VALUE $noreg
- DBG_INSTR_REF 13, 0, !11, !DIExpression(), debug-location !12
- ; CHECK-NEXT: DBG_INSTR_REF 13, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(13, 0), debug-location !12
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(13, 0)
; CHECK-NEXT: DBG_VALUE $noreg
$rax = MOV64rm $rsp, 1, $noreg, 8, $noreg :: (load 8 from %stack.0)
RET64 $rax, debug-location !12
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
index 14c95f35fef80..e55f6993a5b82 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
@@ -171,6 +171,6 @@ body: |
CALL64r %37, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $al, debug-location !13
ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !13
%13:gr32 = INC32r %6, implicit-def dead $eflags, debug-instr-number 1, debug-location !13
- DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
JMP_1 %bb.1, debug-location !13
...
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
index f204094c3288c..db8bd10990564 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-load-folding.mir
@@ -111,7 +111,7 @@ body: |
%7:gr32 = nofpexcept CVTTSS2SIrr killed %1, implicit $mxcsr, debug-instr-number 1
%8:gr8 = COPY killed %7.sub_8bit
- DBG_INSTR_REF 2, 0, !6, !DIExpression(), debug-location !17
+ DBG_INSTR_REF !6, !DIExpression(), dbg-instr-ref(2, 0), debug-location !17
TEST8rr killed %8, %8, implicit-def $eflags
JCC_1 %bb.3, 5, implicit killed $eflags
JMP_1 %bb.2
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
index 2f19ad527ab75..e6d51c2b7bd6b 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/memory-operand-tracking.mir
@@ -52,26 +52,26 @@ body: |
MOV64mr $rsp, 1, $noreg, 16, $noreg, $rdi :: (store 8 into %stack.0)
$rax = MOV64ri 0, debug-location !12
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 3, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0)
- DBG_INSTR_REF 2, 0, !11, !DIExpression(), debug-location !12
- ; CHECK: DBG_INSTR_REF 2, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(2, 0), debug-location !12
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $rsp
;; Test that the old value (from the DBG_PHI) is not tracked anywhere. It
;; should not be considered as being on the stack any more.
- DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
- ; CHECK: DBG_INSTR_REF 1, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: DBG_VALUE $noreg
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-location !12 :: (store (s32) into %stack.0)
;; The above INC32m should be detected as clobbering the stack location,
;; even though it isn't debug labelled.
- DBG_INSTR_REF 2, 0, !11, !DIExpression(), debug-location !12
- ; CHECK: DBG_INSTR_REF 2, 0
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(2, 0), debug-location !12
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK-NEXT: DBG_VALUE $noreg
;; Store another debug-labelled value to the stack,
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 5, debug-location !DILocation(line: 0, scope: !7) :: (store (s32) into %stack.0)
;; Point the variable at that value.
- DBG_INSTR_REF 4, 0, !11, !DIExpression(), debug-location !12
- ; CHECK: DBG_INSTR_REF 4, 0,
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(4, 0), debug-location !12
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0),
; CHECK-NEXT: DBG_VALUE $rsp
;; Overwrite the stack: LiveDebugValues should explicitly undef the stack
;; location with DBG_VALUE $noreg, as DbgEntityHistoryCalculator doesn't
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
index 2a03f07af9845..7752f8059ab2f 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
@@ -17,14 +17,14 @@
# CHECK-LABEL: bb.1.if.then.i.i.i.i.i:
# CHECK: DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]],
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 64, 64)
-# CHECK: DBG_INSTR_REF {{.*}} ![[FIRSTVAR]],
+# CHECK: DBG_INSTR_REF ![[FIRSTVAR]],
# CHECK: DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]],
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 64, 64)
# CHECK-LABEL: bb.2._Z17do_insert_cv_testI5_TreeEvv.exit:
# CHECK: DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]],
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 64, 64)
-# CHECK: DBG_INSTR_REF {{.*}} ![[FIRSTVAR]],
+# CHECK: DBG_INSTR_REF ![[FIRSTVAR]],
# CHECK: DBG_VALUE $rbx, $noreg, ![[FIRSTVAR]],
# CHECK-SAME: !DIExpression(DW_OP_LLVM_fragment, 64, 64)
@@ -118,7 +118,7 @@ body: |
renamable $r14d = XOR32rr undef $r14d, undef $r14d, implicit-def dead $eflags, implicit-def $r14
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi
CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $eax, implicit-def dead $rdx
- DBG_INSTR_REF 2, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !15
+ DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(2, 0), debug-location !15
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi, debug-location !15
CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def dead $al, debug-location !15
TEST8rr renamable $r14b, renamable $r14b, implicit-def $eflags, implicit killed $r14
@@ -128,13 +128,13 @@ body: |
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi
CALL64r undef renamable $rax, csr_64, implicit $rsp, implicit $ssp, implicit killed $rdi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, debug-instr-number 3
$rbx = MOV64rr killed $rax
- DBG_INSTR_REF 3, 7, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !15
+ DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(3, 7), debug-location !15
bb.2._Z17do_insert_cv_testI5_TreeEvv.exit:
liveins: $rbx
DBG_PHI $rbx, 1
- DBG_INSTR_REF 1, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location !15
+ DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location !15
dead $edi = XOR32rr undef $edi, undef $edi, implicit-def dead $eflags, implicit-def $rdi, debug-location !16
$esi = XOR32rr undef $esi, undef $esi, implicit-def dead $eflags, debug-location !16
$rdx = MOV64rr killed $rbx, debug-location !16
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
index b6df94a0b8c2c..bee2975368bbb 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir
@@ -144,7 +144,7 @@ body: |
bb.2.if.end:
%2:gr16 = PHI %11, %bb.0, %17, %bb.1, debug-instr-number 1, debug-location !13
; CHECK: DBG_PHI $bp, 1
- DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
%31:gr32 = MOVSX32rr16 %6, debug-location !13
%30:gr32 = MOVSX32rr16 killed %2, debug-location !13
%29:gr32 = ADD32rr killed %30, killed %31, implicit-def $eflags, debug-location !13
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
index 76eae532109e2..2cff265ab7680 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir
@@ -147,7 +147,7 @@ body: |
bb.2.if.end:
%2:gr64 = PHI %9, %bb.0, %10, %bb.1, debug-instr-number 1, debug-location !13
; CHECK: DBG_PHI $r14, 1
- DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
+ DBG_INSTR_REF !12, !DIExpression(), dbg-instr-ref(1, 0), debug-location !13
%2:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
$rdi = COPY %2, debug-location !13
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
index a0b6d796ce64c..c8096be6b0303 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced.mir
@@ -146,9 +146,9 @@ body: |
%64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
INLINEASM &"", 1, 12, %50, 12, %51, 12, %52, 12, %53, 12, %54, 12, %55, 12, %56, 12, %57, 12, %58, 12, %59, 12, %60, 12, %61, 12, %62, 12, %63, 12, %64
- DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12
+ DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
; CHECK: DBG_PHI %stack.0, 1, 16
- ; CHECK: DBG_INSTR_REF 1, 0
+ ; CHECK: DBG_INSTR_REF {{.+}} dbg-instr-ref(1, 0)
; CHECK: renamable $eax = MOV32rm %stack.0,
$eax = COPY killed %0, debug-location !19
RET 0, killed $eax, debug-location !19
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
index 1047c005a5ad6..8768836a0b2ca 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-on-stack-coalesced2.mir
@@ -145,9 +145,9 @@ body: |
%64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
INLINEASM &"", 1, 12, %50, 12, %51, 12, %52, 12, %53, 12, %54, 12, %55, 12, %56, 12, %57, 12, %58, 12, %59, 12, %60, 12, %61, 12, %62, 12, %63, 12, %64
- DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12
+ DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
; CHECK-NOT: DBG_PHI
- ; CHECK: DBG_INSTR_REF 1, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NOT: DBG_PHI
$eax = COPY killed %0, debug-location !19
RET 0, killed $eax, debug-location !19
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
index f8733e1128f95..7ccfbd42443cd 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir
@@ -139,10 +139,10 @@ body: |
%63:gr32 = PHI %23, %bb.0, %43, %bb.1, debug-location !18
%64:gr32 = PHI %24, %bb.0, %44, %bb.1, debug-location !18
- DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12
+ DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
; CHECK: DBG_PHI %stack.1, 1, 32
; CHECK: renamable $eax = MOV32rm %stack.1,
- ; CHECK: DBG_INSTR_REF 1, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
$eax = COPY killed %0, debug-location !19
RET 0, killed $eax, debug-location !19
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir b/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
index 0e56a79c0930a..9ecd7e46c36ef 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir
@@ -120,9 +120,9 @@ body: |
; CHECK-LABEL: bb.2.if.end:
bb.2.if.end:
%0:gr32 = PHI %1, %bb.0, %2, %bb.1, debug-instr-number 1, debug-location !18
- DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12
+ DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
; CHECK: DBG_PHI $ebp, 1
- ; CHECK: DBG_INSTR_REF 1, 0
+ ; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
$eax = COPY killed %0, debug-location !19
; Confirm that %0 is allocated in $ebp,
; CHECK: $eax = COPY killed renamable $ebp
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir b/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir
index f43ae955bcd33..d969102bf8c46 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/pick-vphi-in-shifting-loop.mir
@@ -12,7 +12,7 @@
# in block 5.
#
# CHECK-LABEL: bb.3:
-# CHECK: DBG_INSTR_REF 7, 0
+# CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
# CHECK-NEXT: DBG_VALUE $rdx
# CHECK-NEXT: $rcx = MOV64rr $rdx
# CHECK-LABEL: bb.4:
@@ -91,7 +91,7 @@ body: |
liveins: $rcx, $rdi, $rdx, $eflags
DBG_PHI $rcx, 2
- DBG_INSTR_REF 2, 0, !18, !DIExpression(), debug-location !22
+ DBG_INSTR_REF !18, !DIExpression(), dbg-instr-ref(2, 0), debug-location !22
JCC_1 %bb.1, 4, implicit $eflags, debug-location !22
bb.2:
@@ -105,7 +105,7 @@ body: |
liveins: $rcx, $rdi, $eflags
$rdx = MOV64ri 0, debug-instr-number 7, debug-location !22
- DBG_INSTR_REF 7, 0, !18, !DIExpression(), debug-location !22
+ DBG_INSTR_REF !18, !DIExpression(), dbg-instr-ref(7, 0), debug-location !22
$rcx = MOV64rr $rdx
JMP_1 %bb.5, debug-location !22
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir b/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir
index 7969fafabc788..7f1d25e42962a 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/spill-slot-limits.mir
@@ -25,10 +25,10 @@
# CHECK: DBG_VALUE $noreg
#
## Test that if there's no limit, we _do_ get some locations.
-# NOLIMIT: DBG_INSTR_REF 1, 0
+# NOLIMIT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
# NOLIMIT-NEXT: DBG_VALUE $esi
#
-# NOLIMIT: DBG_INSTR_REF 5,
+# NOLIMIT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5,
# NOLIMIT-NEXT: DBG_VALUE $rsp
--- |
define i8 @test(i32 %bar) local_unnamed_addr !dbg !7 {
@@ -75,7 +75,7 @@ body: |
$rax = MOV64ri 0
$rdi = MOV64ri 0
- DBG_INSTR_REF 1, 0, !11, !DIExpression(), debug-location !12
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(1, 0), debug-location !12
; This shouldn't find anything -- we have disabled tracking of spills.
; In addition to plain spills, spills that are folded into instructions
@@ -83,7 +83,7 @@ body: |
INC32m $rsp, 1, $noreg, 4, $noreg, implicit-def dead $eflags, debug-instr-number 5, debug-location !12 :: (store (s32) into %stack.0)
- DBG_INSTR_REF 5, 1000000, !11, !DIExpression(), debug-location !12
+ DBG_INSTR_REF !11, !DIExpression(), dbg-instr-ref(5, 1000000), debug-location !12
; Shouldn't be able to find the reference to instr 5's memory operand.
RET64 $rsi, debug-location !12
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
index d9540a7eb4b08..2079ec7305370 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
@@ -219,7 +219,7 @@ body: |
;AAAAAA %4:gr32 = PHI %0, %bb.11, %10, %bb.21, debug-instr-number 1
;BBBBBB %4:gr32 = PHI %0, %bb.11, %10, %bb.21
%5:gr32 = PHI undef %35:gr32, %bb.11, %9, %bb.21
- ;AAAAAA DBG_INSTR_REF 1, 0, !10, !DIExpression(), debug-location !9
+ ;AAAAAA DBG_INSTR_REF !10, !DIExpression(), dbg-instr-ref(1, 0), debug-location !9
;BBBBBB DBG_VALUE %4, 0, !10, !DIExpression(), debug-location !9
%39:gr8 = COPY %27.sub_8bit
TEST8rr killed %39, %39, implicit-def $eflags, debug-location !9
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir b/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
index a5c5018b8434f..daa4b385815fd 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir
@@ -7,7 +7,7 @@
# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
#
# CHECK: MOV64rr $rdi, debug-instr-number 2
-# CHECK-NEXT: DBG_INSTR_REF 1, 0
+# CHECK-NEXT: DBG_INSTR_REF dbg-instr-ref(1, 0)
---
name: test
tracksRegLiveness: true
@@ -19,7 +19,7 @@ body: |
bb.0:
liveins: $rdi, $rax
$rbp = MOV64rr $rdi, debug-instr-number 2
- DBG_INSTR_REF 1, 0
+ DBG_INSTR_REF dbg-instr-ref(1, 0)
dead $rcx = MOV64ri 0
CMP64ri8 renamable $rax, 1, implicit-def $eflags
RET64 $rax
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir b/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
index 53658d2fb53c6..2c9808027fff3 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/survives-livedebugvars.mir
@@ -6,16 +6,16 @@
# livedebugvars-crossbb-interval.mir.
#
# CHECK-LABEL: bb.0:
-# CHECK: DBG_INSTR_REF 1, 0
+# CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
# CHECK-NEXT: JMP_1
# CHECK-LABEL: bb.1:
-# CHECK: DBG_INSTR_REF 2, 0
+# CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
# CHECK-NEXT: JMP_1
# CHECK-LABEL: bb.2:
-# CHECK: DBG_INSTR_REF 3, 0
+# CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
# CHECK-NEXT: CALL64pcrel32
# CHECK-LABEL: bb.3:
-# CHECK: DBG_INSTR_REF 4, 0
+# CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
# CHECK-NEXT: JMP_1
#
#
@@ -24,23 +24,23 @@
# the DBG_INSTR_REF lands on.
#
# FASTREG-LABEL: bb.0:
-# FASTREG-DAG: DBG_INSTR_REF 1, 0
+# FASTREG-DAG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
# FASTREG-DAG: MOV64mr
# FASTREG-DAG: MOV32mr
# FASTREG-NEXT: JMP_1
# FASTREG-LABEL: bb.1:
-# FASTREG: DBG_INSTR_REF 2, 0
+# FASTREG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
# FASTREG-NEXT: JMP_1
# FASTREG-LABEL: bb.2:
-# FASTREG: DBG_INSTR_REF 3, 0
+# FASTREG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
# FASTREG-NEXT: CALL64pcrel32
# FASTREG-LABEL: bb.3:
# FASTREG-DAG: MOV32rm
-# FASTREG-DAG: DBG_INSTR_REF 4, 0
+# FASTREG-DAG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
# FASTREG-DAG: MOV32mr
# FASTREG-NEXT: JMP_1
# FASTREG-LABEL: bb.4:
-# FASTREG: DBG_INSTR_REF 5, 0
+# FASTREG: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
# FASTREG-NEXT: RET64
--- |
@@ -112,18 +112,18 @@ body: |
%2:gr64 = COPY $rdi
%3:gr64 = COPY killed %2
%5:gr32 = COPY killed %4
- DBG_INSTR_REF 1, 0, !9, !DIExpression(), debug-location !16
+ DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(1, 0), debug-location !16
JMP_1 %bb.3
bb.1:
- DBG_INSTR_REF 2, 0, !9, !DIExpression(), debug-location !16
+ DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(2, 0), debug-location !16
JMP_1 %bb.4
bb.2:
ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !19
$edi = COPY %6, debug-location !19
$al = MOV8ri 0, debug-location !19
- DBG_INSTR_REF 3, 0, !9, !DIExpression(), debug-location !16
+ DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(3, 0), debug-location !16
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $ssp, implicit $al, implicit $edi, implicit-def $eax, debug-location !19
ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !19
%7:gr32 = COPY $eax, debug-location !19
@@ -131,12 +131,12 @@ body: |
bb.3:
%6:gr32 = MOV32rm %3, 1, $noreg, 0, $noreg, debug-location !17
- DBG_INSTR_REF 4, 0, !9, !DIExpression(), debug-location !16
+ DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(4, 0), debug-location !16
JMP_1 %bb.2
bb.4:
$eax = COPY %5, debug-location !18
- DBG_INSTR_REF 5, 0, !9, !DIExpression(), debug-location !16
+ DBG_INSTR_REF !9, !DIExpression(), dbg-instr-ref(5, 0), debug-location !16
RET64 implicit $eax, debug-location !18
...
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir b/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
index 561f73524bd06..6df5dbe8cc322 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir
@@ -13,7 +13,7 @@
# CHECK: LEA64_32r
# CHECK-SAME: debug-instr-number 2
#
-# CHECK: DBG_INSTR_REF 1, 0
+# CHECK: DBG_INSTR_REF dbg-instr-ref(1, 0)
---
name: test1
alignment: 16
@@ -34,7 +34,7 @@ body: |
%0:gr32 = COPY killed $edi
%1:gr32 = SHL32ri killed %0, 5, implicit-def dead $eflags
%2:gr32 = ADD32ri8_DB killed %1, 3, implicit-def dead $eflags, debug-instr-number 1
- DBG_INSTR_REF 1, 0
+ DBG_INSTR_REF dbg-instr-ref(1, 0)
$eax = COPY killed %2
RET 0, killed $eax
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir b/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
index f56eddc563db5..42907a676f966 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
@@ -142,8 +142,8 @@ body: |
CALLpcrel32 &_chkstk, implicit $esp, implicit $ssp, implicit $eax, implicit $esp, implicit-def dead $eax, implicit-def $esp, implicit-def dead $eflags, debug-instr-number 2, debug-location !41
$ebx = MOV32rr $esp, debug-location !41
$eax = MOV32ri 0
- DBG_INSTR_REF 2, 6, !42, !DIExpression(DW_OP_deref), debug-location !46
- ; CHECK-LABEL: DBG_INSTR_REF 2, 6
+ DBG_INSTR_REF !42, !DIExpression(DW_OP_deref), dbg-instr-ref(2, 6), debug-location !46
+ ; CHECK-LABEL: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 6)
; CHECK: DBG_VALUE $esp
;; Variable value is $esp / $ebx, will be based on $esp initially. We'll now
@@ -158,15 +158,15 @@ body: |
; CHECK-NEXT: CALLpcrel32
; CHECK-NEXT: DBG_VALUE $ebx
- DBG_INSTR_REF 3, 6, !42, !DIExpression(DW_OP_deref), debug-location !46
- ; CHECK-NEXT: DBG_INSTR_REF 3, 6
+ DBG_INSTR_REF !42, !DIExpression(DW_OP_deref), dbg-instr-ref(3, 6), debug-location !46
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 6)
; CHECK-NEXT: DBG_VALUE $esp
$esp = ADD32ri killed $esp, 0, implicit-def dead $eflags
; CHECK-NEXT: ADD32ri
- DBG_INSTR_REF 3, 6, !42, !DIExpression(DW_OP_deref), debug-location !46
- ; CHECK-NEXT: DBG_INSTR_REF 3, 6
+ DBG_INSTR_REF !42, !DIExpression(DW_OP_deref), dbg-instr-ref(3, 6), debug-location !46
+ ; CHECK-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 6)
; CHECK-NEXT: DBG_VALUE $noreg
$esp = MOV32rr $ebp, debug-location !49
diff --git a/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir b/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
index 0a56d8a615b8c..6fe833d57cd69 100644
--- a/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
+++ b/llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
@@ -82,7 +82,7 @@ body: |
%0:gr64 = MOV64rm killed %1, 1, $noreg, 0, $noreg, debug-location !7 :: (load (s64) from `i8** undef`)
%2:gr32 = COPY %0.sub_32bit, debug-location !7
%3:gr32 = SUB32rm %2, %0, 1, $noreg, 0, $noreg, implicit-def $eflags, debug-instr-number 1, debug-location !7 :: (load (s32) from %ir._M_start.i2756, align 8)
- DBG_INSTR_REF 1, 0, !8, !DIExpression(), debug-location !7
+ DBG_INSTR_REF !8, !DIExpression(), dbg-instr-ref(1, 0), debug-location !7
JCC_1 %bb.2, 5, implicit $eflags, debug-location !7
JMP_1 %bb.1, debug-location !7
diff --git a/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir b/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
index 68be72dcd4ed9..5fe6218c6cd96 100644
--- a/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
+++ b/llvm/test/DebugInfo/MIR/X86/instr-ref-join-def-vphi.mir
@@ -197,7 +197,7 @@ body: |
DBG_PHI $esi, 3
DBG_PHI $edi, 2
- DBG_INSTR_REF 3, 0, !14, !DIExpression(), debug-location !16
+ DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(3, 0), debug-location !16
CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !19
renamable $edi = nsw SUB32rr killed renamable $edi, killed renamable $eax, implicit-def dead $eflags, debug-instr-number 1, debug-location !19
renamable $eax = IMUL32rri renamable $edi, -1431655765, implicit-def dead $eflags, debug-location !21
@@ -211,7 +211,7 @@ body: |
CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !22
renamable $esi = nsw ADD32rr killed renamable $esi, killed renamable $eax, implicit-def dead $eflags, debug-instr-number 4, debug-location !22
- DBG_INSTR_REF 4, 0, !14, !DIExpression(), debug-location !16
+ DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(4, 0), debug-location !16
JMP_1 %bb.3
bb.4 (%ir-block.16):
@@ -226,7 +226,7 @@ body: |
liveins: $esi
CALL64pcrel32 @"?bar@@YAHXZ", csr_win64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !31
- DBG_INSTR_REF 5, 0, !14, !DIExpression(), debug-location !16
+ DBG_INSTR_REF !14, !DIExpression(), dbg-instr-ref(5, 0), debug-location !16
bb.6 (%ir-block.22):
liveins: $esi
diff --git a/llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll b/llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll
index eb7a06728f8b4..89c3e44a1dfb3 100644
--- a/llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll
+++ b/llvm/test/DebugInfo/X86/dbg-value-arg-movement.ll
@@ -61,7 +61,7 @@
; INSTRREF: DBG_PHI $edi, 1
; INSTRREF: DBG_VALUE $edi, $noreg, [[BAZVAR]]
; INSTRREF-LABEL: bb.1.next
-; INSTRREF: DBG_INSTR_REF 1, 0, [[XYZVAR]],
+; INSTRREF: DBG_INSTR_REF [[XYZVAR]], {{.+}}, dbg-instr-ref(1, 0)
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/DebugInfo/X86/dbg-value-funcarg.ll b/llvm/test/DebugInfo/X86/dbg-value-funcarg.ll
index f1edf095e90f7..a2ce754a8e780 100644
--- a/llvm/test/DebugInfo/X86/dbg-value-funcarg.ll
+++ b/llvm/test/DebugInfo/X86/dbg-value-funcarg.ll
@@ -61,7 +61,7 @@ define dso_local void @foo_local(i32 %t1a) local_unnamed_addr #0 !dbg !7 {
; INSTRREF-NEXT: DBG_VALUE 123, $noreg, ![[LOCAL]], !DIExpression(),
; INSTRREF: CALL64pcrel32 @bar,
; INSTRREF-NEXT: ADJCALLSTACKUP64
-; INSTRREF: DBG_INSTR_REF 1, 0, ![[LOCAL]], !DIExpression(),
+; INSTRREF: DBG_INSTR_REF ![[LOCAL]], !DIExpression(), dbg-instr-ref(1, 0),
; INSTRREF-NOT: DBG_
; INSTRREF: TCRETURNdi64 @bar,
@@ -96,7 +96,7 @@ define dso_local void @foo_other_param(i32 %t2a, i32 %t2b) local_unnamed_addr #0
; INSTRREF: CALL64pcrel32 @bar,
; INSTRREF: DBG_VALUE 123, $noreg, ![[T2B]], !DIExpression(),
; INSTRREF: CALL64pcrel32 @bar,
-; INSTRREF: DBG_INSTR_REF 1, 0, ![[T2B]], !DIExpression(),
+; INSTRREF: DBG_INSTR_REF ![[T2B]], !DIExpression(), dbg-instr-ref(1, 0),
; INSTRREF: TCRETURNdi64 @bar,
entry:
@@ -125,10 +125,10 @@ define dso_local void @foo_same_param(i32 %t3a) local_unnamed_addr #0 !dbg !31 {
; INSTRREF: DBG_PHI $edi, 1
; INSTRREF: DBG_VALUE $edi, $noreg, ![[T3A]], !DIExpression(),
; INSTRREF: CALL64pcrel32 @bar,
-; INSTRREF: DBG_INSTR_REF 1, 0, ![[TMP]], !DIExpression(),
+; INSTRREF: DBG_INSTR_REF ![[TMP]], !DIExpression(), dbg-instr-ref(1, 0),
; INSTRREF: DBG_VALUE 123, $noreg, ![[T3A]], !DIExpression(),
; INSTRREF: CALL64pcrel32 @bar,
-; INSTRREF: DBG_INSTR_REF 1, 0, ![[T3A]], !DIExpression(),
+; INSTRREF: DBG_INSTR_REF ![[T3A]], !DIExpression(), dbg-instr-ref(1, 0),
; INSTRREF: TCRETURNdi64 @bar,
entry:
call void @llvm.dbg.value(metadata i32 %t3a, metadata !33, metadata !DIExpression()), !dbg !35
diff --git a/llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll b/llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll
index 7e34213448a6f..970f1db46cdea 100644
--- a/llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll
+++ b/llvm/test/DebugInfo/X86/dbg-value-funcarg2.ll
@@ -60,8 +60,8 @@ define dso_local i32 @f(i64 %s1.coerce0, i64 %s1.coerce1, i64 %s2.coerce0, i64 %
;; of the earlier DBG_PHIs.
; INSTRREF: ADJCALLSTACKUP
; INSTRREF-NOT: DBG_
-; INSTRREF-DAG: DBG_INSTR_REF 1, 0, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 0, 64)
-; INSTRREF-DAG: DBG_INSTR_REF 2, 0, ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 64, 64)
+; INSTRREF-DAG: DBG_INSTR_REF ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 0, 64), dbg-instr-ref(1, 0)
+; INSTRREF-DAG: DBG_INSTR_REF ![[S1]], !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(2, 0)
; And then no more DBG_ instructions before the add.
; COMMON-NOT: DBG_
diff --git a/llvm/test/DebugInfo/X86/dbg-value-funcarg4.ll b/llvm/test/DebugInfo/X86/dbg-value-funcarg4.ll
index df52a39a3497d..af3e317787574 100644
--- a/llvm/test/DebugInfo/X86/dbg-value-funcarg4.ll
+++ b/llvm/test/DebugInfo/X86/dbg-value-funcarg4.ll
@@ -9,8 +9,8 @@
; CHECK: DBG_PHI $edi, 1
-; CHECK: DBG_INSTR_REF 1, 0, ![[LOCAL]], !DIExpression(),
-; CHECK: DBG_INSTR_REF 1, 0, ![[LOCAL2]], !DIExpression(),
+; CHECK: DBG_INSTR_REF ![[LOCAL]], !DIExpression(), dbg-instr-ref(1, 0)
+; CHECK: DBG_INSTR_REF ![[LOCAL2]], !DIExpression(), dbg-instr-ref(1, 0)
declare void @bar(i32)
declare void @llvm.dbg.value(metadata, metadata, metadata)
diff --git a/llvm/test/DebugInfo/X86/instr-ref-dbg-declare.ll b/llvm/test/DebugInfo/X86/instr-ref-dbg-declare.ll
index 97b9bf1324470..3954151091324 100644
--- a/llvm/test/DebugInfo/X86/instr-ref-dbg-declare.ll
+++ b/llvm/test/DebugInfo/X86/instr-ref-dbg-declare.ll
@@ -11,7 +11,7 @@
;; NB: the original test has an additional spurious DW_OP_deref in the
;; dbg.declare's arguments, which is preserved here, translating to two derefs.
-; CHECK: DBG_INSTR_REF 1, 2, !{{[0-9]+}}, !DIExpression(DW_OP_deref, DW_OP_deref)
+; CHECK: DBG_INSTR_REF !{{[0-9]+}}, !DIExpression(DW_OP_deref, DW_OP_deref), dbg-instr-ref(1, 2)
source_filename = "test/DebugInfo/COFF/types-array-advanced.ll"
target datalayout = "e-m:x-p:32:32-i64:64-f80:32-n8:16:32-a:0:32-S32"
diff --git a/llvm/test/DebugInfo/X86/instr-ref-dyn-alloca-win32.ll b/llvm/test/DebugInfo/X86/instr-ref-dyn-alloca-win32.ll
index aa6c87b54efbb..e1f9e7ebf56a9 100644
--- a/llvm/test/DebugInfo/X86/instr-ref-dyn-alloca-win32.ll
+++ b/llvm/test/DebugInfo/X86/instr-ref-dyn-alloca-win32.ll
@@ -13,7 +13,7 @@
;; The alloca instruction should be labelled, and we should refer to operand 2,
;; which happens to be a def of $esp
; DYN_LABEL: DYN_ALLOCA_32 {{.*}} debug-instr-number 1,
-; DYN_LABEL: DBG_INSTR_REF 1, 2
+; DYN_LABEL: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 2)
;; Once lowered, on win32 _chkstk alters the stack pointer. We should label the
;; call and it's SP operand, plus check for a value substitution.
diff --git a/llvm/test/DebugInfo/X86/instr-ref-ir-reg-read.ll b/llvm/test/DebugInfo/X86/instr-ref-ir-reg-read.ll
index 228c0a369e488..958fd0e7adc8f 100644
--- a/llvm/test/DebugInfo/X86/instr-ref-ir-reg-read.ll
+++ b/llvm/test/DebugInfo/X86/instr-ref-ir-reg-read.ll
@@ -9,7 +9,7 @@
; Just examine to see that we read something from $rsp.
; CHECK-LABEL: bb.1.if.then:
; CHECK: DBG_PHI $rsp, 1
-; CHECK: DBG_INSTR_REF 1, 0
+; CHECK: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
source_filename = "tlb-9e7172.c"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/DebugInfo/X86/instr-ref-sdag-empty-vreg.ll b/llvm/test/DebugInfo/X86/instr-ref-sdag-empty-vreg.ll
index 64e1e8ea605b2..fc53edbbba12a 100644
--- a/llvm/test/DebugInfo/X86/instr-ref-sdag-empty-vreg.ll
+++ b/llvm/test/DebugInfo/X86/instr-ref-sdag-empty-vreg.ll
@@ -7,7 +7,7 @@
;; vreg that is never defined, which risks a crash. Check that we don't crash,
;; and produce an empty variable location.
-; CHECK: DBG_VALUE $noreg
+; CHECK: DBG_VALUE_LIST {{.+}}, $noreg
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-unknown"
diff --git a/llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll b/llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll
index 2f9f00ca594b4..79ce92b567cc9 100644
--- a/llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll
+++ b/llvm/test/DebugInfo/X86/instr-ref-selectiondag.ll
@@ -37,10 +37,10 @@
; INSTRREF: ADD32rr
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; INSTRREF-NEXT: ADD32rr
; INSTRREF-SAME: debug-instr-number 2
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; Test that fast-isel will produce DBG_INSTR_REFs too.
@@ -48,10 +48,10 @@
; FASTISEL-INSTRREF: ADD32rr
; FASTISEL-INSTRREF-SAME: debug-instr-number 1
-; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF 1, 0
+; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; FASTISEL-INSTRREF-NEXT: ADD32rr
; FASTISEL-INSTRREF-SAME: debug-instr-number 2
-; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF 2, 0
+; FASTISEL-INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
@glob32 = global i32 0
@glob16 = global i16 0
@@ -107,9 +107,9 @@ entry:
;; Don't test the location of these instr-refs, only that the three non-argument
;; dbg.values become DBG_INSTR_REFs. We previously checked that these numbers
;; get substituted, with appropriate subregister qualifiers.
-; INSTRREF: DBG_INSTR_REF 2, 0
-; INSTRREF: DBG_INSTR_REF 4, 0
-; INSTRREF: DBG_INSTR_REF 6, 0
+; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
+; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
+; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
;; In fast-isel, we get four DBG_INSTR_REFs (compared to three and one
;; DBG_VALUE with normal isel). We get additional substitutions as a result:
@@ -129,10 +129,10 @@ entry:
; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 2
; FASTISEL-INSTRREF-NEXT: DBG_PHI $rdi, 1
-; FASTISEL-INSTRREF: DBG_INSTR_REF 1, 0
-; FASTISEL-INSTRREF: DBG_INSTR_REF 3, 0
-; FASTISEL-INSTRREF: DBG_INSTR_REF 6, 0
-; FASTISEL-INSTRREF: DBG_INSTR_REF 10, 0
+; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
+; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
+; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
+; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(10, 0)
define i32 @bar(i64 %bar) !dbg !20 {
entry:
@@ -172,7 +172,7 @@ entry:
; INSTRREF-NEXT: - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 6, subreg: 4 }
; INSTRREF: CALL64pcrel32 target-flags(x86-plt) @xyzzy, csr_64, implicit $rsp, implicit $ssp, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, debug-instr-number 1
-; INSTRREF: DBG_INSTR_REF 2, 0
+; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
;; Fast-isel produces the same arrangement, a DBG_INSTR_REF pointing back to
;; the call instruction. However: the operand numbers are
diff erent (6 for
@@ -186,7 +186,7 @@ entry:
; FASTISEL-INSTRREF-NEXT: - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 4, subreg: 4 }
; FASTISEL-INSTRREF: CALL64pcrel32 target-flags(x86-plt) @xyzzy, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax, debug-instr-number 1
-; FASTISEL-INSTRREF: DBG_INSTR_REF 2, 0
+; FASTISEL-INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
declare i64 @xyzzy()
@@ -231,17 +231,17 @@ shoes:
; INSTRREF: DBG_PHI $rdi, 1
; INSTRREF-NEXT: DBG_VALUE $rdi, 0, ![[SOCKS]], !DIExpression(),
; INSTRREF-NEXT: %0:gr64 = COPY $rdi
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[KNEES]], !DIExpression(DW_OP_deref),
+; INSTRREF-NEXT: DBG_INSTR_REF ![[KNEES]], !DIExpression(DW_OP_deref), dbg-instr-ref(1, 0),
; In fast-isel mode, neither variable are hoisted or forwarded to a physreg.
; FASTISEL-INSTRREF-LABEL: name: qux
; FASTISEL-INSTRREF: DBG_PHI $rdi, 1
-; FASTISEL-INSTRREF: DBG_INSTR_REF 1, 0, ![[SOCKS]], !DIExpression(DW_OP_deref),
+; FASTISEL-INSTRREF: DBG_INSTR_REF ![[SOCKS]], !DIExpression(DW_OP_deref), dbg-instr-ref(1, 0),
; FASTISEL-INSTRREF-LABEL: bb.1.lala:
-; FASTISEL-INSTRREF: DBG_INSTR_REF 1, 0, ![[KNEES]], !DIExpression(DW_OP_deref),
+; FASTISEL-INSTRREF: DBG_INSTR_REF ![[KNEES]], !DIExpression(DW_OP_deref), dbg-instr-ref(1, 0),
declare i64 @cheddar(ptr %arg)
define void @qux(ptr noalias sret(i32) %agg.result) !dbg !40 {
diff --git a/llvm/test/DebugInfo/X86/pr34545.ll b/llvm/test/DebugInfo/X86/pr34545.ll
index 634cad2e17a61..f4ecce8db447b 100644
--- a/llvm/test/DebugInfo/X86/pr34545.ll
+++ b/llvm/test/DebugInfo/X86/pr34545.ll
@@ -9,17 +9,17 @@
; CHECK: $eax = MOV32rm
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF: DBG_INSTR_REF 1, 0
+; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; CHECK: DBG_VALUE $eax
; CHECK: $eax = SHL32rCL killed renamable $eax,
; INSTRREF-SAME: debug-instr-number 2
-; INSTRREF: DBG_INSTR_REF 2, 0
+; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(2, 0)
; CHECK: DBG_VALUE $eax
; CHECK: DBG_VALUE $rsp, 0, !{{[0-9]+}}, !DIExpression(DW_OP_constu, 4, DW_OP_minus)
; VARLOCS: DBG_VALUE $eax
; CHECK: $eax = SHL32rCL killed renamable $eax,
; INSTRREF-SAME: debug-instr-number 3
-; INSTRREF: DBG_INSTR_REF 3, 0
+; INSTRREF: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
; CHECK: DBG_VALUE $eax
; CHECK: RET64 $eax
diff --git a/llvm/test/DebugInfo/X86/pr40427.ll b/llvm/test/DebugInfo/X86/pr40427.ll
index 777db13bc780f..fe5bc4a5470fb 100644
--- a/llvm/test/DebugInfo/X86/pr40427.ll
+++ b/llvm/test/DebugInfo/X86/pr40427.ll
@@ -30,7 +30,7 @@ block:
; CHECK-NEXT: [[LOADR:%[0-9]+]]:gr16 = MOV16rm %0,
; INSTRREF-SAME: debug-instr-number 1
; DBGVALUE-NEXT: DBG_VALUE [[LOADR]], $noreg, ![[DBGVAR]]
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[DBGVAR]]
+; INSTRREF-NEXT: DBG_INSTR_REF ![[DBGVAR]], {{.+}}, dbg-instr-ref(1, 0)
; CHECK-NEXT: %{{[0-9]+}}:gr32 = IMPLICIT_DEF
%foo = phi ptr[%bees, %trueb], [%more, %falseb]
%ret = load i32, ptr %foo, !dbg !6
diff --git a/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll b/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
index 13ed558642ebc..aaa530df72678 100644
--- a/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
+++ b/llvm/test/DebugInfo/X86/sdag-dangling-dbgvalue.ll
@@ -73,7 +73,7 @@ define i32 @test1() local_unnamed_addr #0 !dbg !17 {
; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[BAR1]], !DIExpression()
; CHECK-NEXT: [[REG1:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO1]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO1]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg, ![[FOO1]], !DIExpression()
entry1:
call void @llvm.dbg.value(metadata ptr @S, metadata !20, metadata !DIExpression()), !dbg !23
@@ -86,8 +86,8 @@ define i32 @test2() local_unnamed_addr #0 !dbg !26 {
; CHECK-LABEL: bb.0.entry2
; CHECK-NEXT: [[REG2:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO2]], !DIExpression()
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR2]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO2]], !DIExpression(), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR2]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[FOO2]], !DIExpression
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[BAR2]], !DIExpression
entry2:
@@ -101,8 +101,8 @@ define i32 @test3() local_unnamed_addr #0 !dbg !33 {
; CHECK-LABEL: bb.0.entry3
; CHECK-NEXT: [[REG3:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR3]], !DIExpression()
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO3]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR3]], !DIExpression(), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO3]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[BAR3]], !DIExpression()
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[FOO3]], !DIExpression()
entry3:
@@ -118,7 +118,7 @@ define i32 @test4() local_unnamed_addr #0 !dbg !40 {
; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[FOO4]], !DIExpression()
; CHECK-NEXT: [[REG4:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR4]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR4]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, ![[BAR4]], !DIExpression()
entry4:
call void @llvm.dbg.value(metadata ptr @S, metadata !42, metadata !DIExpression()), !dbg !44
@@ -134,7 +134,7 @@ define i32 @test5() local_unnamed_addr #0 !dbg !47 {
; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[FOO5]], !DIExpression()
; CHECK-NEXT: [[REG5:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR5]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR5]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG5]], $noreg, ![[BAR5]], !DIExpression()
; CHECK-NOT: DBG_{{.*}} ![[FOO5]], !DIExpression()
; CHECK: RET
diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll
index 76385be4573ac..9d87f7b03c7df 100644
--- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll
+++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll
@@ -55,7 +55,7 @@ for.cond.cleanup: ; preds = %for.body, %entry
; CHECK-LABEL: bb.{{.*}}.for.cond.cleanup:
; CHECK: [[REG1:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 7
-; INSTRREF-NEXT: DBG_INSTR_REF 7, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]]
%x.0.lcssa = phi i32 [ 9, %entry ], [ %add, %for.body ]
call void @llvm.dbg.value(metadata i32 %x.0.lcssa, metadata !15, metadata !DIExpression()), !dbg !26
@@ -72,9 +72,9 @@ for.body: ; preds = %for.body.lr.ph, %fo
; INSTRREF-SAME: debug-instr-number 4
; CHECK-NEXT: [[REG4:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 5
-; INSTRREF-NEXT: DBG_INSTR_REF 3, 0
-; INSTRREF-NEXT: DBG_INSTR_REF 4, 0
-; INSTRREF-NEXT: DBG_INSTR_REF 5, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(3, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(4, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(5, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]]
; DBGVALUE-NEXT: DBG_VALUE [[REG3]]
; DBGVALUE-NEXT: DBG_VALUE [[REG4]]
diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll
index 962564c8e607a..0047e816855bc 100644
--- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll
+++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll
@@ -34,7 +34,7 @@ for.cond.cleanup: ; preds = %for.body, %entry
; CHECK-LABEL: bb.{{.*}}.for.cond.cleanup:
; CHECK: [[REG1:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 7
-; INSTRREF-NEXT: DBG_INSTR_REF 7, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(7, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]]
%x.0.lcssa = phi i32 [ 9, %entry ], [ %add, %for.body ]
call void @llvm.dbg.value(metadata i32 %x.0.lcssa, metadata !15, metadata !DIExpression()), !dbg !26
@@ -51,27 +51,27 @@ for.body: ; preds = %for.body.lr.ph, %fo
; INSTRREF-SAME: debug-instr-number 3
; CHECK-NEXT: [[REG4:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 6
-; INSTRREF-NEXT: DBG_INSTR_REF 3, 0, !16
+; INSTRREF-NEXT: DBG_INSTR_REF !16, {{.+}}, dbg-instr-ref(3, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !16
; CHECK-NEXT: DBG_VALUE 555, $noreg, !17
; CHECK-NEXT: [[ADDREG:%[0-9]+]]:gr32 = nuw nsw ADD32rr
; INSTRREF-SAME: debug-instr-number 5
-; INSTRREF-NEXT: DBG_INSTR_REF 4, 0, !17
+; INSTRREF-NEXT: DBG_INSTR_REF !17, {{.+}}, dbg-instr-ref(4, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !17
; CHECK: [[MULREG:%[0-9]+]]:gr32 = LEA64_32r
; INSTRREF-SAME: debug-instr-number 1
; CHECK-NEXT: DBG_VALUE 777, $noreg, !17
;;; XXX: The following DBG_INSTR_REF should have stayed below the INC32r
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, !16
+; INSTRREF-NEXT: DBG_INSTR_REF !16, {{.+}}, dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[MULREG]], $noreg, !16
; CHECK-NEXT: [[INCREG:%[0-9]+]]:gr32 = nuw nsw INC32r
; INSTRREF-SAME: debug-instr-number 2
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, !17
-; INSTRREF-NEXT: DBG_INSTR_REF 5, 0, !15
+; INSTRREF-NEXT: DBG_INSTR_REF !17, {{.+}}, dbg-instr-ref(2, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !15, {{.+}}, dbg-instr-ref(5, 0)
; DBGVALUE-NEXT: DBG_VALUE [[INCREG]], $noreg, !17
; DBGVALUE-NEXT: DBG_VALUE [[ADDREG]], $noreg, !15
; CHECK-NEXT: implicit-def $eflags,
-; INSTRREF-NEXT: DBG_INSTR_REF 6, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(6, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG4]]
%u.023 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
%y.022 = phi i32 [ 13, %for.body.lr.ph ], [ %mul, %for.body ]
diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll
index 3f99243999794..9a2dc13b129e6 100644
--- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll
+++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll
@@ -75,12 +75,12 @@ for.body: ; preds = %for.body.lr.ph, %fo
; INSTRREF-SAME: debug-instr-number 9
; CHECK-NEXT: [[REG7:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 10
-; INSTRREF-NEXT: DBG_INSTR_REF 5, 0, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 6, 0, !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 7, 0, !18, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 8, 0, !18, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 9, 0, !17, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 10, 0, !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
+; INSTRREF-NEXT: DBG_INSTR_REF !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(5, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(6, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(7, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(8, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !17, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(9, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !17, !DIExpression(DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(10, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !19, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, !18, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
index df83cd4424c56..214a689e0bd49 100644
--- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
+++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll
@@ -19,11 +19,11 @@
; INSTRREF-SAME: debug-instr-number 2
; CHECK-NEXT: [[REG3:%[0-9]+]]:gr32 = PHI
; INSTRREF-SAME: debug-instr-number 3
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 3, 0, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 16)
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, !12, !DIExpression(DW_OP_LLVM_fragment, 10, 32)
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, !12, !DIExpression(DW_OP_LLVM_fragment, 42, 13)
+; INSTRREF-NEXT: DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 32, 32), dbg-instr-ref(2, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !13, !DIExpression(DW_OP_LLVM_fragment, 64, 16), dbg-instr-ref(3, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_fragment, 10, 32), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF !12, !DIExpression(DW_OP_LLVM_fragment, 42, 13), dbg-instr-ref(2, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 0, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 32, 32)
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, !13, !DIExpression(DW_OP_LLVM_fragment, 64, 16)
diff --git a/llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll b/llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
index 97b891c0fe681..7de231300af46 100644
--- a/llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
+++ b/llvm/test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll
@@ -30,7 +30,7 @@ nextbb:
%2 = mul i32 %0, %arg1, !dbg !26
; CHECK: IMUL32rr
call void @llvm.dbg.value(metadata i32 %1, metadata !16, metadata !DIExpression()), !dbg !27
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE
br label %exit, !dbg !26
diff --git a/llvm/test/DebugInfo/X86/sdag-ir-salvage.ll b/llvm/test/DebugInfo/X86/sdag-ir-salvage.ll
index 709092ee26168..57da7044c791b 100644
--- a/llvm/test/DebugInfo/X86/sdag-ir-salvage.ll
+++ b/llvm/test/DebugInfo/X86/sdag-ir-salvage.ll
@@ -14,7 +14,7 @@
; CHECK-LABEL: bb.0.entry:
; INSTRREF: DBG_PHI $rdi, 1
; CHECK-LABEL: bb.1.next:
-; INSTRREF: DBG_INSTR_REF 1, 0, ![[AAAVAR]]
+; INSTRREF: DBG_INSTR_REF ![[AAAVAR]], {{.+}}, dbg-instr-ref(1, 0)
; DBGVALUE: DBG_VALUE %{{[0-9]+}}, $noreg, ![[AAAVAR]]
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/DebugInfo/X86/sdag-salvage-add.ll b/llvm/test/DebugInfo/X86/sdag-salvage-add.ll
index a051f959dc4d8..8be1a6de15c20 100644
--- a/llvm/test/DebugInfo/X86/sdag-salvage-add.ll
+++ b/llvm/test/DebugInfo/X86/sdag-salvage-add.ll
@@ -34,13 +34,15 @@
; CHECK: ![[MYVAR:.*]] = !DILocalVariable(name: "myVar",
; CHECK: $rax = MOV64rm
; INSTRREF-SAME: debug-instr-number 2,
-; INSTRREF-NEXT: DBG_INSTR_REF 2, 0, ![[S4]],
+; INSTRREF-NEXT: DBG_INSTR_REF ![[S4]],
; DBGVALUE-NEXT: DBG_VALUE $rax, $noreg, ![[MYVAR]],
; CHECK-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
+; INSTRREF-SAME: dbg-instr-ref(2, 0)
-; INSTRREF: DBG_INSTR_REF 2, 0, ![[MYVAR]],
+; INSTRREF: DBG_INSTR_REF ![[MYVAR]],
; DBGVALUE: DBG_VALUE $rax, $noreg, ![[S4]],
; CHECK-SAME: !DIExpression(DW_OP_plus_uconst, 4096, DW_OP_stack_value)
+; INSTRREF-SAME: dbg-instr-ref(2, 0)
; CHECK-NEXT: $rdi = MOV64rm killed renamable $rax, 1, $noreg, 4096, $noreg,
source_filename = "test.c"
diff --git a/llvm/test/DebugInfo/X86/sdag-transfer-dbgvalue.ll b/llvm/test/DebugInfo/X86/sdag-transfer-dbgvalue.ll
index cb4e2448018d0..a0f839eadf53c 100644
--- a/llvm/test/DebugInfo/X86/sdag-transfer-dbgvalue.ll
+++ b/llvm/test/DebugInfo/X86/sdag-transfer-dbgvalue.ll
@@ -24,7 +24,7 @@ target triple = "x86_64-unknown-linux-gnu"
; CHECK-LABEL: bb.0.entry:
; CHECK: %[[REG:[0-9]+]]:gr32 = ADD32ri %1, 512,
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE %[[REG]]
; Function Attrs: nofree norecurse nounwind uwtable writeonly
diff --git a/llvm/test/DebugInfo/assignment-tracking/X86/loop-sink.ll b/llvm/test/DebugInfo/assignment-tracking/X86/loop-sink.ll
index 5257d2cf6048e..b3025bed11c2b 100644
--- a/llvm/test/DebugInfo/assignment-tracking/X86/loop-sink.ll
+++ b/llvm/test/DebugInfo/assignment-tracking/X86/loop-sink.ll
@@ -27,7 +27,7 @@
; CHECK: CALL64pcrel32 @getInt{{.*}}debug-instr-number 1
; CHECK-LABEL: bb.2.while.body:
-; CHECK: DBG_INSTR_REF 1, 6, ![[A]], !DIExpression()
+; CHECK: DBG_INSTR_REF ![[A]], !DIExpression(), dbg-instr-ref(1, 6)
; CHECK-LABEL: bb.3.while.end:
; CHECK: MOV32mr %stack.0.a.addr, 1, $noreg, 0, $noreg, %1
diff --git a/llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll b/llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll
index 84b4c8a571727..164f060162a4f 100644
--- a/llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll
+++ b/llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll
@@ -49,7 +49,7 @@
; DBGVALUE: %2:gr64 = nsw ADD64ri8 %1, 2, implicit-def dead $eflags, debug-location
; DBGVALUE-NEXT: DBG_VALUE %2, $noreg, ![[VAR]], !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location
; INSTRREF: %2:gr64 = nsw ADD64ri8 %1, 2, implicit-def dead $eflags, debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[VAR]], !DIExpression(DW_OP_LLVM_fragment, 64, 64), debug-location
+; INSTRREF-NEXT: DBG_INSTR_REF ![[VAR]], !DIExpression(DW_OP_LLVM_fragment, 64, 64), dbg-instr-ref(1, 0), debug-location
source_filename = "test.cpp"
target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll b/llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll
index f581453c8e91c..64ede9c80a005 100644
--- a/llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll
+++ b/llvm/test/DebugInfo/assignment-tracking/X86/sdag-dangling-dbgassign.ll
@@ -79,7 +79,7 @@ define i32 @test1() local_unnamed_addr #0 !dbg !17 {
; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[BAR1]], !DIExpression()
; CHECK-NEXT: [[REG1:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO1]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO1]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG1]], $noreg, ![[FOO1]], !DIExpression()
entry1:
call void @llvm.dbg.assign(metadata ptr @S, metadata !20, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !23
@@ -92,8 +92,8 @@ define i32 @test2() local_unnamed_addr #0 !dbg !26 {
; CHECK-LABEL: bb.0.entry2
; CHECK-NEXT: [[REG2:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO2]], !DIExpression()
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR2]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO2]], !DIExpression(), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR2]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[FOO2]], !DIExpression
; DBGVALUE-NEXT: DBG_VALUE [[REG2]], $noreg, ![[BAR2]], !DIExpression
entry2:
@@ -107,8 +107,8 @@ define i32 @test3() local_unnamed_addr #0 !dbg !33 {
; CHECK-LABEL: bb.0.entry3
; CHECK-NEXT: [[REG3:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR3]], !DIExpression()
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[FOO3]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR3]], !DIExpression(), dbg-instr-ref(1, 0)
+; INSTRREF-NEXT: DBG_INSTR_REF ![[FOO3]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[BAR3]], !DIExpression()
; DBGVALUE-NEXT: DBG_VALUE [[REG3]], $noreg, ![[FOO3]], !DIExpression()
entry3:
@@ -125,7 +125,7 @@ define i32 @test4() local_unnamed_addr #0 !dbg !40 {
; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[FOO4]], !DIExpression()
; CHECK-NEXT: [[REG4:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR4]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR4]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG4]], $noreg, ![[BAR4]], !DIExpression()
entry4:
call void @llvm.dbg.assign(metadata ptr @S, metadata !42, metadata !DIExpression(), metadata !54, metadata ptr undef, metadata !DIExpression()), !dbg !44
@@ -141,7 +141,7 @@ define i32 @test5() local_unnamed_addr #0 !dbg !47 {
; CHECK-NEXT: DBG_VALUE 0, $noreg, ![[FOO5]], !DIExpression()
; CHECK-NEXT: [[REG5:%[0-9]+]]:gr64 = LEA64r
; INSTRREF-SAME: debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0, ![[BAR5]], !DIExpression()
+; INSTRREF-NEXT: DBG_INSTR_REF ![[BAR5]], !DIExpression(), dbg-instr-ref(1, 0)
; DBGVALUE-NEXT: DBG_VALUE [[REG5]], $noreg, ![[BAR5]], !DIExpression()
; CHECK-NOT: DBG_{{.*}} ![[FOO5]], !DIExpression()
; CHECK: RET
diff --git a/llvm/test/DebugInfo/assignment-tracking/X86/sdag-ir-salvage-assign.ll b/llvm/test/DebugInfo/assignment-tracking/X86/sdag-ir-salvage-assign.ll
index f7b06a80562c0..7b8338220372b 100644
--- a/llvm/test/DebugInfo/assignment-tracking/X86/sdag-ir-salvage-assign.ll
+++ b/llvm/test/DebugInfo/assignment-tracking/X86/sdag-ir-salvage-assign.ll
@@ -19,7 +19,7 @@
; CHECK-LABEL: bb.0.entry:
; INSTRREF: DBG_PHI $rdi, 1
; CHECK-LABEL: bb.1.next:
-; INSTRREF: DBG_INSTR_REF 1, 0, ![[AAAVAR]]
+; INSTRREF: DBG_INSTR_REF ![[AAAVAR]], {{.+}}, dbg-instr-ref(1, 0)
; DBGVALUE: DBG_VALUE %{{[0-9]+}}, $noreg, ![[AAAVAR]]
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/DebugInfo/assignment-tracking/X86/sdag-transfer-dbgassign.ll b/llvm/test/DebugInfo/assignment-tracking/X86/sdag-transfer-dbgassign.ll
index 5d5a30641a130..ef5b704a22230 100644
--- a/llvm/test/DebugInfo/assignment-tracking/X86/sdag-transfer-dbgassign.ll
+++ b/llvm/test/DebugInfo/assignment-tracking/X86/sdag-transfer-dbgassign.ll
@@ -30,7 +30,7 @@ target triple = "x86_64-unknown-linux-gnu"
; DBGVALUE: %[[REG:[0-9]+]]:gr32 = ADD32ri %1, 512
; DBGVALUE-NEXT: DBG_VALUE %[[REG]]
; INSTRREF: ADD32ri %1, 512, {{.*}}debug-instr-number 1
-; INSTRREF-NEXT: DBG_INSTR_REF 1, 0
+; INSTRREF-NEXT: DBG_INSTR_REF {{.+}}, dbg-instr-ref(1, 0)
; Function Attrs: nofree norecurse nounwind uwtable writeonly
define dso_local i32 @foo(i32 %a, ptr nocapture %b) local_unnamed_addr !dbg !7 {
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