[PATCH] D141120: [WebAssembly][NFC] Add test case for PR59626

[Luke Lau via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGb599a30e931e: [WebAssembly][NFC] Add test case for PR59626 (authored by luke).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141120/new/

https://reviews.llvm.org/D141120

Files:
  llvm/test/CodeGen/WebAssembly/pr59626.ll


Index: llvm/test/CodeGen/WebAssembly/pr59626.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/WebAssembly/pr59626.ll
@@ -0,0 +1,91 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=wasm32-- -mattr=+simd128 | FileCheck --check-prefix=CHECK-32 %s
+; RUN: llc < %s -mtriple=wasm64-- -mattr=+simd128 | FileCheck --check-prefix=CHECK-64 %s
+
+define i8 @f(ptr %0, ptr %1) {
+; CHECK-32-LABEL: f:
+; CHECK-32:         .functype f (i32, i32) -> (i32)
+; CHECK-32-NEXT:    .local v128
+; CHECK-32-NEXT:  # %bb.0: # %BB
+; CHECK-32-NEXT:    local.get 0
+; CHECK-32-NEXT:    i32.const 0
+; CHECK-32-NEXT:    i32.store8 2
+; CHECK-32-NEXT:    local.get 0
+; CHECK-32-NEXT:    v128.const 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-32-NEXT:    v128.store16_lane 0, 0
+; CHECK-32-NEXT:    local.get 1
+; CHECK-32-NEXT:    i32.const 5
+; CHECK-32-NEXT:    v128.const 0, 0
+; CHECK-32-NEXT:    i32x4.extract_lane 0
+; CHECK-32-NEXT:    i8x16.splat
+; CHECK-32-NEXT:    v128.const 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
+; CHECK-32-NEXT:    v128.and
+; CHECK-32-NEXT:    local.tee 2
+; CHECK-32-NEXT:    i8x16.extract_lane_u 2
+; CHECK-32-NEXT:    i32.div_u
+; CHECK-32-NEXT:    i32.store8 2
+; CHECK-32-NEXT:    local.get 1
+; CHECK-32-NEXT:    i32.const 1
+; CHECK-32-NEXT:    local.get 2
+; CHECK-32-NEXT:    i8x16.extract_lane_u 0
+; CHECK-32-NEXT:    local.tee 0
+; CHECK-32-NEXT:    i32.const 1
+; CHECK-32-NEXT:    i32.and
+; CHECK-32-NEXT:    i32.div_u
+; CHECK-32-NEXT:    i8x16.splat
+; CHECK-32-NEXT:    i32.const 3
+; CHECK-32-NEXT:    local.get 2
+; CHECK-32-NEXT:    i8x16.extract_lane_u 1
+; CHECK-32-NEXT:    i32.div_u
+; CHECK-32-NEXT:    i8x16.replace_lane 1
+; CHECK-32-NEXT:    v128.store16_lane 0, 0
+; CHECK-32-NEXT:    local.get 0
+; CHECK-32-NEXT:    # fallthrough-return
+;
+; CHECK-64-LABEL: f:
+; CHECK-64:         .functype f (i64, i64) -> (i32)
+; CHECK-64-NEXT:    .local v128, i32
+; CHECK-64-NEXT:  # %bb.0: # %BB
+; CHECK-64-NEXT:    local.get 0
+; CHECK-64-NEXT:    i32.const 0
+; CHECK-64-NEXT:    i32.store8 2
+; CHECK-64-NEXT:    local.get 0
+; CHECK-64-NEXT:    v128.const 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+; CHECK-64-NEXT:    v128.store16_lane 0, 0
+; CHECK-64-NEXT:    drop
+; CHECK-64-NEXT:    local.get 1
+; CHECK-64-NEXT:    i32.const 5
+; CHECK-64-NEXT:    v128.const 0, 0
+; CHECK-64-NEXT:    i32x4.extract_lane 0
+; CHECK-64-NEXT:    i8x16.splat
+; CHECK-64-NEXT:    v128.const 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1
+; CHECK-64-NEXT:    v128.and
+; CHECK-64-NEXT:    local.tee 2
+; CHECK-64-NEXT:    i8x16.extract_lane_u 2
+; CHECK-64-NEXT:    i32.const 1
+; CHECK-64-NEXT:    i32.and
+; CHECK-64-NEXT:    i32.div_u
+; CHECK-64-NEXT:    i32.store8 2
+; CHECK-64-NEXT:    local.get 1
+; CHECK-64-NEXT:    i32.const 1
+; CHECK-64-NEXT:    local.get 2
+; CHECK-64-NEXT:    i8x16.extract_lane_u 0
+; CHECK-64-NEXT:    local.tee 3
+; CHECK-64-NEXT:    i32.const 1
+; CHECK-64-NEXT:    i32.and
+; CHECK-64-NEXT:    i32.div_u
+; CHECK-64-NEXT:    i8x16.splat
+; CHECK-64-NEXT:    v128.store16_lane 0, 0
+; CHECK-64-NEXT:    drop
+; CHECK-64-NEXT:    local.get 3
+; CHECK-64-NEXT:    # fallthrough-return
+BB:
+  store <3 x i8> zeroinitializer, ptr %0
+  %S = shufflevector <3 x i128> zeroinitializer, <3 x i128> <i128 0, i128 1, i128 2>, <3 x i32> undef
+  %C = icmp ule <3 x i128> %S, zeroinitializer
+  %C1 = zext <3 x i1> %C to <3 x i8>
+  %E = extractelement <3 x i8> %C1, i32 0
+  %B = sdiv <3 x i8> <i8 1, i8 3, i8 5>, %C1
+  store <3 x i8> %B, ptr %1
+  ret i8 %E
+}


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