[PATCH] D141101: [AMDGPU] More selectively attach implicit operands to agpr spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added a comment.
This revision is now accepted and ready to land.

LGTM with nit. The verifier will catch the cases that are wrong. I'd still prefer to not do this optimization here in the first place, or at least to avoid direct overlaps checks by using regunit liveness checking



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Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1563
       }
-      if (IsSubReg || NeedSuperRegImpOperand) {
+      if ((IsSubReg ||NeedSuperRegImpOperand) && (IsFirstSubReg || IsLastSubReg)) {
         NeedSuperRegImpOperand = true;
----------------
Lost a space after ||


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D141101/new/

https://reviews.llvm.org/D141101