[PATCH] D140649: [AArch64][SelectionDAG] Eliminates redundant zero-extension for 32-bit popcount

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

Could it just use a FMOVWSr?

  def : Pat<(v8i8 (bitconvert (i64 (zext GPR32:$Rn)))),
            (SUBREG_TO_REG (i32 0), (f32 (FMOVWSr GPR32:$Rn)), ssub)>;

That way we know the top bits will be zero from the FMOVWSr, and so the SUBREG_TO_REG will correctly assert the top bits are zero.


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  https://reviews.llvm.org/D140649/new/

https://reviews.llvm.org/D140649