[PATCH] D140939: [X86] Transform AtomicRMW logic operations to BT{R|C|S} if only changing/testing a single bit.
Phoebe Wang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jan 5 18:36:09 PST 2023
pengfei added inline comments.
================
Comment at: llvm/test/CodeGen/X86/atomic-rm-bit-test.ll:4622-4628
+; X86-NEXT: jae .LBB78_1
+; X86-NEXT: # %bb.2: # %if.then
+; X86-NEXT: movl (%ecx,%eax,4), %eax
+; X86-NEXT: retl
+; X86-NEXT: .LBB78_1:
; X86-NEXT: movl $123, %eax
; X86-NEXT: retl
----------------
goldstein.w.n wrote:
> pengfei wrote:
> > The branch code doesn't look necessary. Can we necessary it?
> > The branch code doesn't look necessary. Can we necessary it?
>
> I think it is b.c we don't `cmovcc` loads.
>
> For
> ```
> if.then: ; preds = %entry
> %idxprom = zext i32 %c to i64
> %arrayidx = getelementptr inbounds i32, ptr %v, i64 %idxprom
> %1 = load i32, ptr %arrayidx, align 4
> br label %return
> ```
>
> And
> ```
> return: ; preds = %entry, %if.then
> %retval.0 = phi i32 [ %1, %if.then ], [ 123, %entry ]
> ret i32 %retval.0
> ```
>
> a branch seems correct.
Sorry for the wrong words. I mean can we eliminate the branch by modifying the IR code, e.g.,
```
entry:
%shl = shl nuw i32 1, %c
%0 = atomicrmw or ptr %v, i32 %shl monotonic, align 4
%and = and i32 %0, %shl
%tobool.not = icmp eq i32 %and, 0
%ret = zext i1 %tobool.not to i32
ret i32 %ret
```
This will help to reduce the nosie in reviewing the code and pay more attention to the change we expected.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D140939/new/
https://reviews.llvm.org/D140939
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