[PATCH] D141075: [SelectionDAG] Implicitly truncate known bits in SPLAT_VECTOR

[Philip Reames via Phabricator via llvm-commits]

reames added a comment.

Test case?



================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:2980
     SDValue SrcOp = Op.getOperand(0);
-    if (SrcOp.getValueSizeInBits() != BitWidth) {
-      assert(SrcOp.getValueSizeInBits() > BitWidth &&
+      assert(SrcOp.getValueSizeInBits() >= BitWidth &&
              "Expected SPLAT_VECTOR implicit truncation");
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It looks like you've got some extra white space here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D141075/new/

https://reviews.llvm.org/D141075