[PATCH] D140509: [DAGCombiner][RISCV] Pre-promote (zext (abs X)) to (abs (sext X)) when X has an illegal type.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/iabs.ll:664
+; RV64I-NEXT:    srai a0, a0, 56
+; RV64I-NEXT:    srai a2, a0, 63
 ; RV64I-NEXT:    xor a0, a0, a2
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craig.topper wrote:
> craig.topper wrote:
> > Looks like we might be missing a DAG combine to fold back to back SRA?
> Nevermind, it's because there is a freeze hiding after the first two shifts.
D136529 should fix this once I've addressed the remaining regressions


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  https://reviews.llvm.org/D140509/new/

https://reviews.llvm.org/D140509